From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp141.iad.emailsrvr.com (smtp141.iad.emailsrvr.com [207.97.245.141]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by huchra.bufferbloat.net (Postfix) with ESMTPS id 2931921F175; Thu, 20 Dec 2012 05:53:14 -0800 (PST) Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp54.relay.iad1a.emailsrvr.com (SMTP Server) with ESMTP id 8FE3A2B0C16; Thu, 20 Dec 2012 08:53:12 -0500 (EST) X-Virus-Scanned: OK Received: from legacy23.wa-web.iad1a (legacy23.wa-web.iad1a.rsapps.net [192.168.4.109]) by smtp54.relay.iad1a.emailsrvr.com (SMTP Server) with ESMTP id 4FFD22B0AE7; Thu, 20 Dec 2012 08:53:12 -0500 (EST) Received: from reed.com (localhost.localdomain [127.0.0.1]) by legacy23.wa-web.iad1a (Postfix) with ESMTP id 3A55610A0001; Thu, 20 Dec 2012 08:53:12 -0500 (EST) Received: by apps.rackspace.com (Authenticated sender: dpreed@reed.com, from: dpreed@reed.com) with HTTP; Thu, 20 Dec 2012 08:53:12 -0500 (EST) Date: Thu, 20 Dec 2012 08:53:12 -0500 (EST) Subject: =?utf-8?Q?Re=3A_=5BCerowrt-devel=5D_hardware_hacking_on_fq=5Fcodel_in_FPG?= =?utf-8?Q?A_form_at_10GigE?= From: dpreed@reed.com To: "Hal Murray" MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_20121220085312000000_25612" Importance: Normal X-Priority: 3 (Normal) X-Type: html In-Reply-To: <20121220103213.4ABAD800037@ip-64-139-1-69.sjc.megapath.net> References: <20121220103213.4ABAD800037@ip-64-139-1-69.sjc.megapath.net> Message-ID: <1356011592.2372508@apps.rackspace.com> X-Mailer: webmail7.0 X-Mailman-Approved-At: Fri, 21 Dec 2012 08:31:29 -0800 Cc: codel@lists.bufferbloat.net, bloat-devel , cerowrt-devel@lists.bufferbloat.net X-BeenThere: bloat-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: "Developers working on AQM, device drivers, and networking stacks" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Dec 2012 13:53:14 -0000 ------=_20121220085312000000_25612 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =0AI have lately been using (for my very wideband software defined radio am= ateur radio transceiver project) the brand new, very nice device called the= Zynq 7000 series of Platform FPGA's from Xilinx. It's a complete system o= n a chip, with a dual core ARM Cortex A9 and an enormous amount of programm= able logic that has "cache coherent access" to the memory system.=0A =0AThe= chip is fabricated in 28 nm form, has a "zillion" SelectIO programmable pi= ns, but more importantly has a bunch of hard logic I/O paths.=0A =0ASince i= t comes packaged "cheap" (full 6 inch square evalboard with 512 MB DRAM an= d full standard "PC type" interconnects - GigE, VGA, HDMI, USB), as a $299 = board with free FPGA tool chain) and runs Linux out of the box, I highly re= commend the board called Zedboard (just google that).=0A =0AEasy to attach = 10 GigE hardware if you can do simple PCB design and soldering.=0A =0AYou c= an be up and running with a development system for under $500 in a weekend,= building FPGA acceleration, or if you want to add hardware that connects t= o the zillions of I/O pins to the PLL and memory system, that might take a = week or more, depending on your hardware design and hacking skills. I've co= nnected "eval boards" of various sorts using a breakout board you can buy f= rom Xilinx quicker than that.=0A =0AIn some ways, this is the Raspberry Pi = of high speed digital logic hacking.=0A =0A =0A =0A =0A-----Original Messag= e-----=0AFrom: "Hal Murray" =0ASent: Thursday, Dec= ember 20, 2012 5:32am=0ATo: "Dave Taht" =0ACc: "bloat-= devel" , codel@lists.bufferbloat.net, "H= al Murray" , cerowrt-devel@lists.bufferbloat.net= =0ASubject: Re: [Cerowrt-devel] hardware hacking on fq_codel in FPGA form a= t 10GigE=0A=0A=0A=0Adave.taht@gmail.com said:=0A>> If I was going to do som= ething like that, I'd build a small/simple CPU=0A>> the work in microcode.= =0A=0A> There are two ppc 440 cpus already onboard the 10GigE device, I thi= nk. It's=0A> a REALLY NICE fpga. =0A=0A> I'd also looked at the octeon and = the latest arm chipset from TI which I=0A> can't remember the codename for = at the moment... =0A=0AI wasn't thinking of a traditional general purpose C= PU but rather something =0Aspecial for this problem.=0A=0A=0A=0A>> How many= lines of assembler code would it take?=0A=0A> I could do a dump of the cur= rent code into any given assembly language. It's=0A> not a lot, but there a= re a lot of out of band functions.=0A=0AI didn't mean lines of traditional = assembly code. If we want to pursue this, =0Apick a chunk of c code (not t= oo big) and break it into "lines" where =0Aeverything on a line can be exec= uted at the same time. I'll try to sketch a =0A"CPU" and write the microco= de.=0A=0A=0A> The enqueue and dequeue algorithms are entirely decoupled, wi= th the=0A> exception of this error handling phase of (out of queue space) O= ne thought=0A> would be to track packet count on enqueue (this is more "sfq= "-like than=0A> fq_codel-like) which still has a tiny lock... =0A=0AStuff t= hat can be reasonably done in the driver should probably be done there =0Ai= f it saves a lot of work for the microcode. Avoiding out-of-queue-space = =0Amight be a good example.=0A=0A=0A=0A> Well there are a few things that w= ould benefit from moving directly into=0A> hardware - the 5 tuple hash, for= example. =0A=0AI'm probably missing the big picture. Are you building a r= outer or a server?=0A=0AA server has socket control blocks. Can the hash b= e precomputed and stored =0Athere?=0AThat doesn't help with UDP sendto, but= I think it would work with TCP.=0A=0A=0AIf you are building a router, does= the routing as well as fq-ing have to fit =0Ain the FPGA?=0A=0A=0A-- =0ATh= ese are my opinions. I hate spam.=0A=0A=0A=0A_____________________________= __________________=0ACerowrt-devel mailing list=0ACerowrt-devel@lists.buffe= rbloat.net=0Ahttps://lists.bufferbloat.net/listinfo/cerowrt-devel ------=_20121220085312000000_25612 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

= I have lately been using (for my very wideband software defined radio amate= ur radio transceiver project) the brand new, very nice device called the Zy= nq 7000 series of Platform FPGA's from Xilinx.  It's a complete system= on a chip, with a dual core ARM Cortex A9 and an enormous amount of progra= mmable logic that has "cache coherent access" to the memory system.

=0A<= p style=3D"margin:0;padding:0;"> 

=0A

The chip is fabricated in 28 nm form, has a "zillion" SelectIO programma= ble pins, but more importantly has a bunch of hard logic I/O paths.

=0A<= p style=3D"margin:0;padding:0;"> 

=0A

Since it comes packaged "cheap" (full  6 inch square evalboard with= 512 MB DRAM and full standard "PC type" interconnects - GigE, VGA, HDMI, U= SB), as a $299 board with free FPGA tool chain) and runs Linux out of the b= ox, I highly recommend the board called Zedboard (just google that).

=0A=

 

=0A

Easy to attach 10 GigE hardware if you can do simple PCB design and sol= dering.

=0A

 

=0A

You can be up and running with a development system for u= nder $500 in a weekend, building FPGA acceleration, or if you want to add h= ardware that connects to the zillions of I/O pins to the PLL and memory sys= tem, that might take a week or more, depending on your hardware design and = hacking skills. I've connected "eval boards" of various sorts using a break= out board you can buy from Xilinx quicker than that.

=0A

 

=0A

In some ways= , this is the Raspberry Pi of high speed digital logic hacking.

=0A

 

=0A

&= nbsp;

=0A

 

=0A

 

=0A

-----Original= Message-----
From: "Hal Murray" <hmurray@megapathdsl.net>
= Sent: Thursday, December 20, 2012 5:32am
To: "Dave Taht" <dave.taht= @gmail.com>
Cc: "bloat-devel" <bloat-devel@lists.bufferbloat.net= >, codel@lists.bufferbloat.net, "Hal Murray" <hmurray@megapathdsl.net= >, cerowrt-devel@lists.bufferbloat.net
Subject: Re: [Cerowrt-devel]= hardware hacking on fq_codel in FPGA form at 10GigE

=0A
dave.taht@gmail.com said:
>> = If I was going to do something like that, I'd build a small/simple CPU
>> the work in microcode.

> There are two ppc 440 cpus= already onboard the 10GigE device, I think. It's
> a REALLY NICE f= pga.

> I'd also looked at the octeon and the latest arm chip= set from TI which I
> can't remember the codename for at the moment= ...

I wasn't thinking of a traditional general purpose CPU but = rather something
special for this problem.



>= ;> How many lines of assembler code would it take?

> I cou= ld do a dump of the current code into any given assembly language. It's
> not a lot, but there are a lot of out of band functions.

= I didn't mean lines of traditional assembly code. If we want to pursue thi= s,
pick a chunk of c code (not too big) and break it into "lines" whe= re
everything on a line can be executed at the same time. I'll try t= o sketch a
"CPU" and write the microcode.


> The e= nqueue and dequeue algorithms are entirely decoupled, with the
> ex= ception of this error handling phase of (out of queue space) One thought> would be to track packet count on enqueue (this is more "sfq"-like = than
> fq_codel-like) which still has a tiny lock...

St= uff that can be reasonably done in the driver should probably be done there=
if it saves a lot of work for the microcode. Avoiding out-of-queue-= space
might be a good example.



> Well there= are a few things that would benefit from moving directly into
> ha= rdware - the 5 tuple hash, for example.

I'm probably missing th= e big picture. Are you building a router or a server?

A server = has socket control blocks. Can the hash be precomputed and stored
th= ere?
That doesn't help with UDP sendto, but I think it would work with= TCP.


If you are building a router, does the routing as we= ll as fq-ing have to fit
in the FPGA?


--
These= are my opinions. I hate spam.



____________________= ___________________________
Cerowrt-devel mailing list
Cerowrt-de= vel@lists.bufferbloat.net
https://lists.bufferbloat.net/listinfo/cerow= rt-devel ------=_20121220085312000000_25612--