Hacking on the rtl8366S

[Dave Taht <dave.taht@gmail.com>]

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I sat down to play with the rtl366S
switch code (which is the one in the wndr3700)
late last night.  Attached is as far as I got, merely

A) some new register definitions

B) support for getting the ip/mac addr of the switch

(I didn't remember the functions for printing them out of the kernel last
night)

C) changing the the default buffer size in the switch to >9k.

I was pleased that I didn't blow anything up, and it compiled and ran the
first time, and for all I know, it did some good (and is already in the
cerowrt build at:

http://huchra.bufferbloat.net/~cerowrt/cerowrt-wndr3700/

Which, of course, includes SFB, and nearly every other debloating trick
we've come up with so far.
)


So I thought I would sit down and explain what I'm trying to accomplish:

0) By *increasing* the per-packet buffer size, I hope that the enormous
latencies (>100ms) in the switch I have been seeing, will reduce
significantly.

In other words, I'm starving the switch of ram it otherwise would use for
buffering.

(threads on this on the bloat lists, documentation on the bismark-testbed
wiki).

Gaining jumbo packet support out of it is just a bonus.

1) The switch has a mac address, which so far as I know, is unused. (the
switch is bridged to the wireless interfaces, normally)

I'd like to be ROUTING packets between wired and wireless, rather than
switching them - at least for now - because it's really hard to make sense
of some of the packet traces I've been seeing without separating the media
they've been running on.

2) *Really* want port mirroring to work - similar reasons to point 1, above.


3)  Interestingly, there is QoS on the switch, which supports diffserv. (as
well as vlan or port based prioritization)

4) Various forms of flow control should be enable-able

5) With better per-port link state info, it might be possible to throttle or
balance flows across those ports better.

6) There's probably other stuff worth doing

Open questions:

How to expose a QoS API to userspace?
Similarly, port mirroring...
How is the snmp mib interface supposed to work?

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diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366s.c b/target/linux/generic/files/drivers/net/phy/rtl8366s.c
index 3f3d6f6..972e9a2 100644
--- a/target/linux/generic/files/drivers/net/phy/rtl8366s.c
+++ b/target/linux/generic/files/drivers/net/phy/rtl8366s.c
@@ -20,7 +20,7 @@
 #include "rtl8366_smi.h"
 
 #define RTL8366S_DRIVER_DESC	"Realtek RTL8366S ethernet switch driver"
-#define RTL8366S_DRIVER_VER	"0.2.2"
+#define RTL8366S_DRIVER_VER	"0.2.3"
 
 #define RTL8366S_PHY_NO_MAX	4
 #define RTL8366S_PHY_PAGE_MAX	7
@@ -46,6 +46,57 @@
 #define RTL8366S_SSCR2				0x0004
 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA		BIT(0)
 
+/* Port Mirroring */
+
+/* The RTL8366/RTL8369 supports one set of port mirroring 
+   functions for all 6/9 ports. User could
+   monitor both the TX and RX packets of the source port from a mirror port. 
+   The source port to be
+   mirrored can be selected in SOURCE_PORT[3:0] in Register PMCR (0x0007). 
+   The monitor port can be
+   selected in MONITOR_PORT[3:0] in Register PMCR (0x0007).
+   MIRROR_TX and MIRROR_RX in Register PMCR (0x0007) are used to select 
+   the TX or RX packets
+   of the source port to be mirrored. 
+   If MIRROR_ISO in Register PMCR (0x0007) is enabled, the monitor
+   port only forwards the TX or RX packets of the source port. 
+   Any other packets destined for the monitor port will be dropped. 
+   When MIRROR_SPC in Register PMCR (0x0007) is enabled,
+   Pause packets received by the source port will be forwarded to the 
+   monitor port.
+
+
+*/
+
+#define RTL8366S_PMCR 				0x0007
+
+#define RTL8366S_MIRROR_SOURCE_PORT 0
+#define RTL8366S_MIRROR_MONITOR_PORT 4
+#define RTL8366S_MIRROR_RX BIT(8)
+#define RTL8366S_MIRROR_TX BIT(9)
+#define RTL8366S_MIRROR_ISO BIT(11)
+#define RTL8366S_MIRROR_SPC BIT(10)
+
+/* QoS Control Registers */
+#define RTL8366S_QCR0				0x0009
+
+/* QCR1 controls port based priority */
+#define RTL8366S_QCR1				0x000A
+
+/* QCR2-5 are there for diffserv */
+#define RTL8366S_QCR2				0x000B
+#define RTL8366S_QCR3				0x000C
+#define RTL8366S_QCR4				0x000D
+#define RTL8366S_QCR5				0x000E
+
+#define RTL8366S_EN_QOS 			BIT(0)
+#define RTL8366S_EN_PORT_PRI 			BIT(2)
+#define RTL8366S_EN_DS_PRI 			BIT(3)
+#define RTL8366S_EN_1Q_PRI			BIT(4)
+
+/* bits 7&6 control the weight */
+#define RTL8366S_QUEUE_WEIGHT 7 
+
 #define RTL8366S_RESET_CTRL_REG			0x0100
 #define RTL8366S_CHIP_CTRL_RESET_HW		1
 #define RTL8366S_CHIP_CTRL_RESET_SW		(1 << 1)
@@ -55,6 +106,15 @@
 #define RTL8366S_CHIP_ID_REG			0x0105
 #define RTL8366S_CHIP_ID_8366			0x8366
 
+/* Switch MAC And IP Addr */
+
+#define RTL8366S_SMAR0				0x0046
+#define RTL8366S_SMAR1				0x0047
+#define RTL8366S_SMAR2				0x0048
+
+#define RTL8366S_SW_IP0				0x004D
+#define RTL8366S_SW_IP1			0x004E
+
 /* PHY registers control */
 #define RTL8366S_PHY_ACCESS_CTRL_REG		0x8028
 #define RTL8366S_PHY_ACCESS_DATA_REG		0x8029
@@ -263,9 +323,9 @@ static int rtl8366s_hw_init(struct rtl8366_smi *smi)
 			       pdata->initvals[i].val);
 	}
 
-	/* set maximum packet length to 1536 bytes */
+	/* set maximum packet length to 16000 bytes */
 	REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
-		RTL8366S_SGCR_MAX_LENGTH_1536);
+		RTL8366S_SGCR_MAX_LENGTH_16000);
 
 	/* enable learning for all ports */
 	REG_WR(smi, RTL8366S_SSCR0, 0);
@@ -690,6 +750,21 @@ static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
 }
 
 
+static int rtl_8366s_get_ip(struct rtl8366_smi *smi) {
+  u32 a, b;
+  rtl8366_smi_read_reg(smi,RTL8366S_SW_IP0,&a);
+  rtl8366_smi_read_reg(smi,RTL8366S_SW_IP1,&b);
+  return(a | b << 16);
+}
+
+static u64 rtl_8366s_get_mac(struct rtl8366_smi *smi) {
+  u64 a, b, c;
+  rtl8366_smi_read_reg(smi,RTL8366S_SMAR0,&a);
+  rtl8366_smi_read_reg(smi,RTL8366S_SMAR1,&b);
+  rtl8366_smi_read_reg(smi,RTL8366S_SMAR2,&c);
+  return(a | b << 16 | c << 32);
+}
+
 static const char *rtl8366s_speed_str(unsigned speed)
 {
 	switch (speed) {
@@ -1001,6 +1076,9 @@ static int rtl8366s_detect(struct rtl8366_smi *smi)
 {
 	u32 chip_id = 0;
 	u32 chip_ver = 0;
+	u32 ip = 0;
+	u64 mac = 0;
+
 	int ret;
 
 	ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
@@ -1027,6 +1105,11 @@ static int rtl8366s_detect(struct rtl8366_smi *smi)
 	dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
 		 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
 
+	ip = rtl_8366s_get_ip(smi);
+	mac = rtl_8366s_get_mac(smi);
+
+	dev_info(smi->parent, "Switch Mac: %ld, Switch IP: %d\n", mac, ip);
+
 	return 0;
 }