From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ie0-f175.google.com (mail-ie0-f175.google.com [209.85.223.175]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority" (verified OK)) by huchra.bufferbloat.net (Postfix) with ESMTPS id 9824021F199; Thu, 20 Dec 2012 01:26:40 -0800 (PST) Received: by mail-ie0-f175.google.com with SMTP id qd14so4134626ieb.6 for ; Thu, 20 Dec 2012 01:26:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=JH8mpHhMJVq7agaIHsswjswz5lXkM+aHhY0NoNuA3Xg=; b=Q+/kDzlve9SCKsNZQksyfzxCqVgP3CPwIQaP0ZoWdjukRI891K3pjGy50ZaWoh1iXd 2WPUobWzoeUpPdfgPO4geIk/fXwxvW2cE4g5L7X9u+kU7r+dzIWxRqEaxJYnOJU25QA/ QfiOWNkk6oFBzye4obudRYo5wCxfonGppCl91BQXMHshdERhwZQDURENGGQidt7iSsV7 3UFqhGE/Rs/5oOiebBo8INc6dHv0EROpGcE2zPgFPPsMcXsv5UGGrEliIGts3DJQ/JDv BZy8SCP3WJk8KOEBnCPdlbrXDrbHBNvdLYRorI/cSrG9phUvBaeK62B+iVJ77PjPdJe7 0Dmg== MIME-Version: 1.0 Received: by 10.50.187.225 with SMTP id fv1mr4901501igc.96.1355995598009; Thu, 20 Dec 2012 01:26:38 -0800 (PST) Received: by 10.64.135.39 with HTTP; Thu, 20 Dec 2012 01:26:37 -0800 (PST) In-Reply-To: References: <20121220081737.1A681800037@ip-64-139-1-69.sjc.megapath.net> Date: Thu, 20 Dec 2012 04:26:37 -0500 Message-ID: Subject: Re: hardware hacking on fq_codel in FPGA form at 10GigE From: Dave Taht To: Hal Murray Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: codel@lists.bufferbloat.net, bloat-devel , cerowrt-devel@lists.bufferbloat.net X-BeenThere: bloat-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: "Developers working on AQM, device drivers, and networking stacks" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Dec 2012 09:26:41 -0000 On Thu, Dec 20, 2012 at 4:13 AM, Dave Taht wrote: > On Thu, Dec 20, 2012 at 3:17 AM, Hal Murray wro= te: >> >> If I was going to do something like that, I'd build a small/simple CPU a= nd do >> the work in microcode. I'd also looked at the octeon and the latest arm chipset from TI which I can't remember the codename for at the moment... http://www.cavium.com/OCTEON-II_CN68XX.html Looks like cavium is going ARM with their next chip. I'd certainly like to see an IP block for arm socs for this stuff too. Given the huge number of offloads in the network path on most upcoming SOCs, it's going to be hard to wedge queue management on top in software. See, for example, the mindspeed C2000. So it seems like finding an arm design house to get an IP block for fq_codel put together is in order. There are a couple interesting hybrid fpga/arm chips from places like st mi= cro. --=20 Dave T=E4ht Fixing bufferbloat with cerowrt: http://www.teklibre.com/cerowrt/subscribe.= html