From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ie0-f181.google.com (mail-ie0-f181.google.com [209.85.223.181]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority" (verified OK)) by huchra.bufferbloat.net (Postfix) with ESMTPS id 5F6DE21F175; Wed, 19 Dec 2012 23:28:20 -0800 (PST) Received: by mail-ie0-f181.google.com with SMTP id 16so4002320iea.40 for ; Wed, 19 Dec 2012 23:28:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type :content-transfer-encoding; bh=QTLXM1Ag5TWBguBCkibLdFHHy6CHkNvf6bB6p5Qt+oM=; b=H252qxX+vFhovuBMtOSEMBpDMME/xnI+eCNcmOnqgEc3D4kSjbyZTpPuiOaqIuXask 5D4y6bs3WPUmHvktJbBctid7vdm3HkxSxz9uimzXsTXK0KRnv3qDYoF/1AcpqS9V5Q88 NYFJUUc5IhzDIBCDnArQ/l3hP/a82RnjFNTcUDRYGIvDiUQUn3YrqSqd2Jn9I1508l+w f8EdsyTQd8ahIqYuUrp5yJbID6diKk5hGW0rc7J34SoO6BZ+8dx6laUIZdTUaW0wPt4n WpegzHWcD9VysAEe8JFv4eFC7aG1O1EVp6fEyTGjkYjNJ+MtqKNDMMfUIA/IrqnNagiM bhMQ== MIME-Version: 1.0 Received: by 10.50.196.164 with SMTP id in4mr4474753igc.86.1355988499435; Wed, 19 Dec 2012 23:28:19 -0800 (PST) Received: by 10.64.135.39 with HTTP; Wed, 19 Dec 2012 23:28:19 -0800 (PST) Date: Thu, 20 Dec 2012 02:28:19 -0500 Message-ID: Subject: hardware hacking on fq_codel in FPGA form at 10GigE From: Dave Taht To: cerowrt-devel@lists.bufferbloat.net, bloat-devel , codel@lists.bufferbloat.net Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-BeenThere: bloat-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: "Developers working on AQM, device drivers, and networking stacks" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Dec 2012 07:28:21 -0000 see: http://netfpga.org/ The quad gig-E version looks like it works well (in that there are advanced things like DRR available for it) but the underlying FPGA is obsolete. The quad 10GigE version looks sexy but not very functional as yet. In either case, implementing {n,e,s}fq_codel onboard looks very feasible, although something of a larger effort than I'd like to spend personally. (it's been about 6 years since I last touched verilog) I would be interested however in getting a bunch of hardware hackers together (and getting the academic discount on this board) to try and do an implementation of a fq_codel derivative on the quad 10GigE board. (or I would be happy to learn of some group already doing it) The only thing that is seriously serial about fq_codel is shooting the biggest flow when the queue limit is exceeded, and that could be made embarrassingly parallel with enough gates.There are no doubt other tricky issues. I would like it if we could match the ns2 model entirely... down to the last packet... in the real world. I have few contacts at stanford, presently. https://mailman.stanford.edu/pipermail/netfpga-announce/2012-October/000094= .html There are a couple of other alternatives in the GigE space and below on openers.... --=20 Dave T=E4ht Fixing bufferbloat with cerowrt: http://www.teklibre.com/cerowrt/subscribe.= html