From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x22d.google.com (mail-lf0-x22d.google.com [IPv6:2a00:1450:4010:c07::22d]) by lists.bufferbloat.net (Postfix) with ESMTPS id EC9E73B2C5 for ; Wed, 6 Jan 2016 01:18:24 -0500 (EST) Received: by mail-lf0-x22d.google.com with SMTP id z124so302235829lfa.3 for ; Tue, 05 Jan 2016 22:18:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=content-type:mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=qY7LCqMft4zGJtWQjwkN04alYkYZjFIuooyu7BSvSWE=; b=VmOcwKCYd5kic37ImPNr7olE7JW1MDC0GZ6Xk1jnPVVpO+YTcx2l4TfzTauqfkYkGh q9AprAM1DUSb2cuNpVE9gxK0z23M6tPDAyxVxI2wqHH7vhvMaSl53yXitY0nJbgoCC1u ZXujRUZtx/1XI2zCDeoM6ImWX4xAZO8oJ/xjjE94fiVrUgLssHhTl6VvkdP1zatJNuGu B9MBko3bLEzMaIHZ6TrlhtrRnvP++OS4gpWEfQaEQVLxFGPAV2OO+4ctumIdTdg+f+Jj qZV+4NIDJi0hAi1heK+x1QAEuxRNExeMsgBd65WbIKf9GUHHFEUmzoXLY9fUGw9Minwf ls8w== X-Received: by 10.25.154.207 with SMTP id c198mr23575924lfe.32.1452061102803; Tue, 05 Jan 2016 22:18:22 -0800 (PST) Received: from bass.home.chromatix.fi (37-33-99-74.bb.dnainternet.fi. [37.33.99.74]) by smtp.gmail.com with ESMTPSA id f74sm2604421lfb.7.2016.01.05.22.18.21 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 Jan 2016 22:18:22 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 9.2 \(3112\)) From: Jonathan Morton In-Reply-To: <20160106002213.GA8486@sesse.net> Date: Wed, 6 Jan 2016 08:18:19 +0200 Cc: Stephen Hemminger , "bloat@lists.bufferbloat.net" Content-Transfer-Encoding: quoted-printable Message-Id: <1AAED798-A2DC-4D90-B51A-7414930C3C21@gmail.com> References: <165DB6E9-A6DD-4626-B6AA-E1B2DBA0B5FA@gmail.com> <568C1209.5050403@taht.net> <20160106000151.GA5332@sesse.net> <20160106002213.GA8486@sesse.net> To: "Steinar H. Gunderson" X-Mailer: Apple Mail (2.3112) Subject: Re: [Bloat] Hardware upticks X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2016 06:18:25 -0000 > On 6 Jan, 2016, at 02:22, Steinar H. Gunderson = wrote: >=20 > On Tue, Jan 05, 2016 at 04:06:03PM -0800, Stephen Hemminger wrote: >> The expensive part is often having to save and restore all the state = in >> registers and other bits on context switch. >=20 > Are you sure? There's not really all that much state to save, and all = I've > been taught before says the opposite. >=20 > Also, I've never ever seen the actual context switch turn up high in a = perf > profile. Is this because of some sampling artifact? ARM has dedicated register banks for several interrupt levels for = exactly this reason. Simple interrupt handlers can operate in these = without spilling *any* userspace registers. This gives ARM quite good = interrupt latency, especially in the simpler implementations. That doesn=E2=80=99t help for an actual context switch of course. What = does help is =E2=80=9Clazy FPU state switching=E2=80=9D, where on a = context switch the FPU is simply marked as unavailable. Only if/when = the process attempts to *use* the FPU, this gets trapped and the trap = handler restores the correct state before returning an enabled FPU to = userspace. The same goes for SIMD register banks, of course. Lazy context switching is a kernel feature. It=E2=80=99s used on all = architectures that have a runtime disable-able FPU, AFAIK. For a = context switch to kernel and back to the same process, the FPU & SIMD = are never actually switched, so there is almost no overhead. - Jonathan Morton