From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-x234.google.com (mail-pf0-x234.google.com [IPv6:2607:f8b0:400e:c00::234]) by lists.bufferbloat.net (Postfix) with ESMTPS id 7F5523B2C7 for ; Tue, 5 Jan 2016 15:26:57 -0500 (EST) Received: by mail-pf0-x234.google.com with SMTP id 65so180601174pff.3 for ; Tue, 05 Jan 2016 12:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=VpEMpQr6EL3QFfJhd2Cl9Bcl+/AXFjyFnWLV8c4fCWA=; b=RhljqZ3/v9kHdNEzH6m7xLtA8uOg9VIG1T/BV5ejoWbQ0FjoZx2gfZvOy550y83M0G bPXBrDpCSNdc5EzT27VjbI5Wk9CcMw+aPDRlUD6+aEkxmMrMg0T6IvTbcVGXFHyWd+Oe 4rncdNnMVgHx0UOYDIS6YM4b7ruxZzQHcoi+/GX1sywNeHzCWhdu/LD9DdXPAhgQS3Xv fHrn714QjLj27Fhsra15CkM12wcv6cTJTfquG+2IPZtsEp76CdK06b5BVCZoCpxgr7tb r82a5L7yt5dwj+MkCvMZBdZnevSTtZhfed+OE3Eyb6kiOmGzGk/EEVZaVl+hFnBHCgxn Rt0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=VpEMpQr6EL3QFfJhd2Cl9Bcl+/AXFjyFnWLV8c4fCWA=; b=b5poQJb18eLUxwcrpi65x0VcPGeAtx4UzGLyXuUogK0ClmWyOOYXLLQmAZhXHWoSHS puhp24Hzq+fr3EJnQ16/iFmZ4HcO2piJGKIFfZBhCzaq3QNKvZGrbkw5as/kDJ/wp6Eo cB3AgcNrWS5v2LkhR1KHuP4yHPYMGBXKrfopBVlImrMcxAbrRqGXAUPzBdYy414JqY39 fOD1V3BrZgIVjP3PTwV+ysHWP+MMPXNlOapm5GCcj40T0T9Uax9NLvWv8RvrGWkpv+YF zKiUr1WH42eFAJYvoZUGyeouH34E63pFTlC1h+f+vgKfvTqVCpxXEcZdeA1bG+cREktE yr8Q== X-Gm-Message-State: ALoCoQkTVVa7oT1yFJbHzqmhuxytuhqS+zlHtKrSgdjq12DFg1uLmIph6UBb5Cnwki2O0mDC0tXd9v/0tfHJS4sXPq5BU1So5A== X-Received: by 10.98.16.83 with SMTP id y80mr62045099pfi.150.1452025615791; Tue, 05 Jan 2016 12:26:55 -0800 (PST) Received: from xeon-e3 (static-50-53-82-155.bvtn.or.frontiernet.net. [50.53.82.155]) by smtp.gmail.com with ESMTPSA id 2sm59002165pfj.16.2016.01.05.12.26.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Jan 2016 12:26:55 -0800 (PST) Date: Tue, 5 Jan 2016 12:27:03 -0800 From: Stephen Hemminger To: Dave =?UTF-8?B?VMOkaHQ=?= Cc: bloat@lists.bufferbloat.net Message-ID: <20160105122703.516b54be@xeon-e3> In-Reply-To: <568C1B5E.1070008@taht.net> References: <165DB6E9-A6DD-4626-B6AA-E1B2DBA0B5FA@gmail.com> <568C1209.5050403@taht.net> <20160105192930.GA7803@sesse.net> <568C1B5E.1070008@taht.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Bloat] Hardware upticks X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2016 20:26:57 -0000 On Tue, 5 Jan 2016 11:37:02 -0800 Dave T=C3=A4ht wrote: >=20 >=20 > On 1/5/16 11:29 AM, Steinar H. Gunderson wrote: > > On Tue, Jan 05, 2016 at 10:57:13AM -0800, Dave T=C3=A4ht wrote: > >> Context switch time is probably one of the biggest hidden nightmares in > >> modern OOO cpu architectures - they only go fast in a straight line. I= 'd > >> love to see a 1ghz processor that could context switch in 5 cycles. > >=20 > > It's called hyperthreading? ;-) > >=20 > > Anyway, the biggest cost of a context switch isn't necessarily the time= used > > to set up registers and such. It's increased L1 pressure; your CPU is n= ow > > running different code and looking at (largely) different data. >=20 > +10. >=20 > A L1/L2 Icache dedicated to interrupt processing code could make a great > deal of difference, if only cpu makers and benchmarkers would make > CS time something we valued. >=20 > Dcache, not so much, except for the intel architectures which are now > doing DMA direct to cache. (any arms doing that?) >=20 > > /* Steinar */ > >=20 > _______________________________________________ > Bloat mailing list > Bloat@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/bloat Intel has some new Cache QoS stuff that allows configuring how much cache is allowed per context. But of course it is only on the newest/lates= t/unoptinium