From: "Steinar H. Gunderson" <sgunderson@bigfoot.com>
To: bloat@lists.bufferbloat.net
Subject: Re: [Bloat] Hardware upticks
Date: Wed, 6 Jan 2016 01:01:51 +0100 [thread overview]
Message-ID: <20160106000151.GA5332@sesse.net> (raw)
In-Reply-To: <CAJ_ENFHA++fSosEY5RDR=82H5XdkQ8P31Nhksrq7OA_Ds_EBZg@mail.gmail.com>
On Tue, Jan 05, 2016 at 03:36:10PM -0600, Benjamin Cronce wrote:
> You can't have different virtual memory space and not take some large
> switching overhead without devoting a lot of transistors to massive caches.
> And the larger the caches, the higher the latency.
I'm sure you already know this, but just to add to what you're saying:
Modern CPUs actually have cache-line tagging tricks so that they don't have
to blow the entire L1 just because you do a context switch. It would be too
expensive.
/* Steinar */
--
Homepage: https://www.sesse.net/
next prev parent reply other threads:[~2016-01-06 0:01 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-05 6:37 Jonathan Morton
2016-01-05 17:42 ` Aaron Wood
2016-01-05 18:27 ` Jonathan Morton
2016-01-05 18:57 ` Dave Täht
2016-01-05 19:29 ` Steinar H. Gunderson
2016-01-05 19:37 ` Dave Täht
2016-01-05 20:13 ` David Collier-Brown
2016-01-05 20:27 ` Stephen Hemminger
2016-01-05 21:10 ` Jonathan Morton
2016-01-05 23:20 ` Steinar H. Gunderson
2016-01-05 23:17 ` Steinar H. Gunderson
2016-01-05 21:36 ` Benjamin Cronce
2016-01-06 0:01 ` Steinar H. Gunderson [this message]
2016-01-06 0:06 ` Stephen Hemminger
2016-01-06 0:22 ` Steinar H. Gunderson
2016-01-06 0:53 ` Stephen Hemminger
2016-01-06 0:55 ` Steinar H. Gunderson
2016-01-06 1:22 ` Stephen Hemminger
2016-01-06 6:18 ` Jonathan Morton
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