From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cassarossa.samfundet.no (cassarossa.samfundet.no [IPv6:2001:67c:29f4::29]) by lists.bufferbloat.net (Postfix) with ESMTPS id CE10B3B2B9 for ; Tue, 5 Jan 2016 19:01:53 -0500 (EST) Received: from yesthisis.dog ([2001:67c:29f4::3007] helo=pannekake.samfundet.no ident=unknown) by cassarossa.samfundet.no with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1aGbXz-0001Tb-GE for bloat@lists.bufferbloat.net; Wed, 06 Jan 2016 01:01:51 +0100 Received: from sesse by pannekake.samfundet.no with local (Exim 4.84) (envelope-from ) id 1aGbXz-0001ho-BI for bloat@lists.bufferbloat.net; Wed, 06 Jan 2016 01:01:51 +0100 Date: Wed, 6 Jan 2016 01:01:51 +0100 From: "Steinar H. Gunderson" To: bloat@lists.bufferbloat.net Message-ID: <20160106000151.GA5332@sesse.net> References: <165DB6E9-A6DD-4626-B6AA-E1B2DBA0B5FA@gmail.com> <568C1209.5050403@taht.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: X-Operating-System: Linux 4.3.0 on a x86_64 User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [Bloat] Hardware upticks X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2016 00:01:54 -0000 On Tue, Jan 05, 2016 at 03:36:10PM -0600, Benjamin Cronce wrote: > You can't have different virtual memory space and not take some large > switching overhead without devoting a lot of transistors to massive caches. > And the larger the caches, the higher the latency. I'm sure you already know this, but just to add to what you're saying: Modern CPUs actually have cache-line tagging tricks so that they don't have to blow the entire L1 just because you do a context switch. It would be too expensive. /* Steinar */ -- Homepage: https://www.sesse.net/