From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from eu1sys200aog103.obsmtp.com (eu1sys200aog103.obsmtp.com [207.126.144.115]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by huchra.bufferbloat.net (Postfix) with ESMTPS id A1E1121F2A1 for ; Tue, 27 May 2014 05:34:19 -0700 (PDT) Received: from mail.la.pnsol.com ([89.145.213.110]) (using TLSv1) by eu1sys200aob103.postini.com ([207.126.147.11]) with SMTP ID DSNKU4SGSZZTwzMvFjSUFZ/BnXaUVyCfEQMr@postini.com; Tue, 27 May 2014 12:34:19 UTC Received: from ba6-office.pnsol.com ([172.20.5.199]) by mail.la.pnsol.com with esmtp (Exim 4.76) (envelope-from ) id 1WpGa8-0006V0-LW; Tue, 27 May 2014 13:34:16 +0100 Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.2\)) From: Neil Davies In-Reply-To: Date: Tue, 27 May 2014 13:34:16 +0100 Content-Transfer-Encoding: quoted-printable Message-Id: <346A4866-BEF9-4371-91AF-D4FEF4CE4A36@pnsol.com> References: <6A1B2B32-DC32-41D8-9BA3-57E28DD18F64@pnsol.com> To: Hagen Paul Pfeifer X-Mailer: Apple Mail (2.1878.2) Cc: bloat@lists.bufferbloat.net Subject: Re: [Bloat] ipspace.net: "QUEUING MECHANISMS IN MODERN SWITCHES" X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 May 2014 12:34:20 -0000 Hagen It comes down to the portion of the end-to-end quality attenuation = (quality attenuation - =E2=88=86Q - incorporates both loss and delay) = budget you want to assign to device and how you want it distributed = amongst the competing flows (given that is all you can do - you can=E2=80=99= t =E2=80=9Cdestroy=E2=80=9D loss or =E2=80=9Cdestroy=E2=80=9D delay, = just differentially distribute it).=20 As for ingress/egress capacity being almost the same, that *REALLY* = depends on the deployment scenario=E2=80=A6. You can=E2=80=99t do traffic performance engineering in a vacuum - you = need to have objectives for the application outcomes - that makes the = problem context dependent.=20 When we do this for people we often find that there are several = locations in the architecture where FIFO is the best solution (where you = can prove that the natural relaxation times of the queues, given the = offered load pattern, is sufficiently small so as not to induce to much = quality attenuation). In other places you need to do more analysis.=10 Neil On 27 May 2014, at 13:20, Hagen Paul Pfeifer wrote: > The question is if (codel/pie/whatever) AQM makes sense at all for > 10G/40G hardware and higher performance irons? Igress/egress bandwidth > is nearly identical, a larger/longer buffering should not happen. Line > card memory is limited, a larger buffering is defacto excluded. >=20 > Are there any documents/papers about high bandwidth equipment and > bufferbloat effects? >=20 > Hagen