From: "Dave Täht" <dave@taht.net>
To: bloat@lists.bufferbloat.net
Subject: Re: [Bloat] Hardware upticks
Date: Tue, 5 Jan 2016 11:37:02 -0800 [thread overview]
Message-ID: <568C1B5E.1070008@taht.net> (raw)
In-Reply-To: <20160105192930.GA7803@sesse.net>
On 1/5/16 11:29 AM, Steinar H. Gunderson wrote:
> On Tue, Jan 05, 2016 at 10:57:13AM -0800, Dave Täht wrote:
>> Context switch time is probably one of the biggest hidden nightmares in
>> modern OOO cpu architectures - they only go fast in a straight line. I'd
>> love to see a 1ghz processor that could context switch in 5 cycles.
>
> It's called hyperthreading? ;-)
>
> Anyway, the biggest cost of a context switch isn't necessarily the time used
> to set up registers and such. It's increased L1 pressure; your CPU is now
> running different code and looking at (largely) different data.
+10.
A L1/L2 Icache dedicated to interrupt processing code could make a great
deal of difference, if only cpu makers and benchmarkers would make
CS time something we valued.
Dcache, not so much, except for the intel architectures which are now
doing DMA direct to cache. (any arms doing that?)
> /* Steinar */
>
next prev parent reply other threads:[~2016-01-05 19:34 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-05 6:37 Jonathan Morton
2016-01-05 17:42 ` Aaron Wood
2016-01-05 18:27 ` Jonathan Morton
2016-01-05 18:57 ` Dave Täht
2016-01-05 19:29 ` Steinar H. Gunderson
2016-01-05 19:37 ` Dave Täht [this message]
2016-01-05 20:13 ` David Collier-Brown
2016-01-05 20:27 ` Stephen Hemminger
2016-01-05 21:10 ` Jonathan Morton
2016-01-05 23:20 ` Steinar H. Gunderson
2016-01-05 23:17 ` Steinar H. Gunderson
2016-01-05 21:36 ` Benjamin Cronce
2016-01-06 0:01 ` Steinar H. Gunderson
2016-01-06 0:06 ` Stephen Hemminger
2016-01-06 0:22 ` Steinar H. Gunderson
2016-01-06 0:53 ` Stephen Hemminger
2016-01-06 0:55 ` Steinar H. Gunderson
2016-01-06 1:22 ` Stephen Hemminger
2016-01-06 6:18 ` Jonathan Morton
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