From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from nm3-vm4.access.bullet.mail.gq1.yahoo.com (nm3-vm4.access.bullet.mail.gq1.yahoo.com [216.39.63.91]) by lists.bufferbloat.net (Postfix) with ESMTPS id 52BCA3B2C6 for ; Tue, 5 Jan 2016 15:13:09 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rogers.com; s=s2048; t=1452024788; bh=FYJ+bDxkerU0W2RuxkvWgq3puQXOWh2eL3+HeHSC+y8=; h=Reply-To:Subject:References:To:From:Date:In-Reply-To:From:Subject; b=h+Fqoql6cCd9eXhWUcY4iDmsjvHMqqvw+U6lMBhBmLXUcgaRAYf8jBTF40dqwsq+8Qm47T42B1zZjUl376MwiP6PgauEoGgCpW2sKQINsy/ICV1D5Zrtgfamz7vcapTKV+WIA4jpLvIsxQoRrOvgeY1WqduATIrL+5dDs+Sio6CP22BHD4S8d/St2tSetFnWABUgpGKjbquxJF17OqVAcIu1t04L64KdkdGrsmzwVt1DTbmJbqx1Nn14SWkeWYLAhwURwIqrq8Mcib1GMwTvzRpvZJBQjFhSKS9eoZgmllklD6B3uKsmlNpHAb85+Q2BhacaDq4P90z7sh14AkPnQg== Received: from [216.39.60.170] by nm3.access.bullet.mail.gq1.yahoo.com with NNFMP; 05 Jan 2016 20:13:08 -0000 Received: from [98.138.104.96] by tm6.access.bullet.mail.gq1.yahoo.com with NNFMP; 05 Jan 2016 20:13:08 -0000 Received: from [127.0.0.1] by smtp116.sbc.mail.ne1.yahoo.com with NNFMP; 05 Jan 2016 20:13:08 -0000 X-Yahoo-Newman-Id: 361872.14923.bm@smtp116.sbc.mail.ne1.yahoo.com X-Yahoo-Newman-Property: ymail-3 X-YMail-OSG: AfWwAhQVM1mzaaHhSsLj813tnyhsMw5rS4dvzlnrgkYQnGt 299FI9DqYvZlL_B6M.UdUKBk0DAdgOP5u1szxwk_O2ZvJIQQB3E5eiIpJvzV fHjgD8RuvYlDld.Y1DoGXG1nfJV6pQMGcdd1N5wmOyPMQDD82Jg3WmxAgXUM aW5oqm.qOIeKtKhicOM8bOFKUMhsfd9KaZ.ISVVujj..KCdfapzrlHcX2LwB .wIYgE11byPKcxtq1v9A3M91WjLSLKozgpvSGKshv6ZiQ27xejn1PXQs1Hh6 Wmk84Y.7vwgL3R9DWK5wXK7I8xBTpU6O847giRJJnsxpD3MmKvUYIYmBIFjt sSCBMKst7zi_CD.9o2u_L4z_DVQC3wHGP6aXv17UxSZpWQ7eeEUqKAgfyezS c.3CXQzjuaIas9XE7seDlopserBclPg7dW01yZkN2L5W7jl0b.grmlbiGluq 0uVEKprAVO2fsnHLy1eeGA08BW2NWzhAxaCfG4a2gYN04n6zEbT2mYg8Abh2 uIgmPvYn3n1SIM3lUSiYcL9r1YA63Uqpb18dSSaRwQyrqaH8G1.RjTfncHtJ vmidrYpc- X-Yahoo-SMTP: sltvjZWswBCRD.ElTuB1l9j6s9wRYPpuyTNWOE5oEg-- Reply-To: davecb@spamcop.net References: <165DB6E9-A6DD-4626-B6AA-E1B2DBA0B5FA@gmail.com> <568C1209.5050403@taht.net> <20160105192930.GA7803@sesse.net> <568C1B5E.1070008@taht.net> To: bloat@lists.bufferbloat.net From: David Collier-Brown Message-ID: <568C23D2.8060708@rogers.com> Date: Tue, 5 Jan 2016 15:13:06 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <568C1B5E.1070008@taht.net> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Bloat] Hardware upticks X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2016 20:13:10 -0000 The SPARC T5 is surprisingly good here, with a very short path to cache and a moderate number of threads with hot cache lines. Cache performance was one of the surprises when the slowish early T-machines came out, and surprised a smarter colleague and I who had apps bottlenecking on cold cache lines on what were nominally much faster processors. I'd love to have a T5-1 on an experimenter board, or perhaps even in my laptop (I used to own a SPARC laptop), but that's not where Snoracle is going. --dave On 05/01/16 02:37 PM, Dave Täht wrote: > > On 1/5/16 11:29 AM, Steinar H. Gunderson wrote: >> On Tue, Jan 05, 2016 at 10:57:13AM -0800, Dave Täht wrote: >>> Context switch time is probably one of the biggest hidden nightmares in >>> modern OOO cpu architectures - they only go fast in a straight line. I'd >>> love to see a 1ghz processor that could context switch in 5 cycles. >> It's called hyperthreading? ;-) >> >> Anyway, the biggest cost of a context switch isn't necessarily the time used >> to set up registers and such. It's increased L1 pressure; your CPU is now >> running different code and looking at (largely) different data. > +10. > > A L1/L2 Icache dedicated to interrupt processing code could make a great > deal of difference, if only cpu makers and benchmarkers would make > CS time something we valued. > > Dcache, not so much, except for the intel architectures which are now > doing DMA direct to cache. (any arms doing that?) > >> /* Steinar */ >> > _______________________________________________ > Bloat mailing list > Bloat@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/bloat -- David Collier-Brown, | Always do right. This will gratify System Programmer and Author | some people and astonish the rest davecb@spamcop.net | -- Mark Twain