Re: [Bloat] known buffer sizes on switches

[Dave Collier-Brown <Dave.Collier-Brown@indexexchange.com>]

On 2018-11-28 11:55 a.m., Dave Taht wrote:

> Thank you for that. I do have a long standing dream of a single chip
> wifi router, with the lowest SNR possible, and the minimum number of
> pins coming off of it. I'd settle for 32MB of (static?) ram on chip as
> that has proven sufficient to date to drive 802.11n....
>
> which would let you get rid of both the L2 and L1 cache. That said, I
> think the cost of 32MB of on-chip static ram remains a bit high, and
> plugging it into a mips cpu, kind of silly. Someday there will be a case
> to just doing everything on a single chip, but...

I could see 32MB or more of fast memory on-chip as being attractive when
one is fighting with diminishing returns in CPU speed and program
parallelizability.

In the past that might have excited MIPS, but these days less so. Maybe
ARM? IBM?

--dave

--
David Collier-Brown,         | Always do right. This will gratify
System Programmer and Author | some people and astonish the rest
dave.collier-brown@indexexchange.com |              -- Mark Twain


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