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From: David Collier-Brown <davec-b@rogers.com>
To: Dave Taht <dave.taht@gmail.com>,
	David Collier-Brown <davecb@spamcop.net>
Cc: bloat <bloat@lists.bufferbloat.net>
Subject: Re: [Bloat] known buffer sizes on switches
Date: Wed, 28 Nov 2018 15:34:53 -0500	[thread overview]
Message-ID: <7b414124-fdd1-e9c7-9c6f-a66049ddcd56@rogers.com> (raw)
In-Reply-To: <CAA93jw4SzN51p2aFi67Ge3wPbheA+jqB9hTt76Ebg0HuoMV5KA@mail.gmail.com>

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That would be really cool: I loved the Mips we had at YorkU.ca

--dave

On 2018-11-28 2:02 p.m., Dave Taht wrote:
> I really don't know a whole heck of a lot about where mips is going.
> Certainly they remain strong in the embedded market (I do like the
> edgerouter X a lot), but as for their current direction or future
> product lines, not a clue.
>
> I used to know someone over there, maybe he's restored new directions.
> Last I recall he was busy obsoleting a whole lot of instruction space
> in order to make room for "new stuff". He'd even asked me if adding an
> invsqrt to the instruction set would help, and I sadly replied that
> that bit of codel was totally invisible on a trace.....
>
> I really like(d) mips. ton of registers, better instruction set than
> arm (IMHO), no foolish processor extensions.
>
> On Wed, Nov 28, 2018 at 10:26 AM David Collier-Brown <davec-b@rogers.com> wrote:
>> On 2018-11-28 11:55 a.m., Dave Taht wrote:
>>
>>> Thank you for that. I do have a long standing dream of a single chip
>>> wifi router, with the lowest SNR possible, and the minimum number of
>>> pins coming off of it. I'd settle for 32MB of (static?) ram on chip as
>>> that has proven sufficient to date to drive 802.11n....
>>>
>>> which would let you get rid of both the L2 and L1 cache. That said, I
>>> think the cost of 32MB of on-chip static ram remains a bit high, and
>>> plugging it into a mips cpu, kind of silly. Someday there will be a case
>>> to just doing everything on a single chip, but...
>> I could see 32MB or more of fast memory on-chip as being attractive when
>> one is fighting with diminishing returns in CPU speed and program
>> parallelizability.
>>
>> In the past that might have excited MIPS, but these days less so. Maybe
>> ARM? IBM?
>>
>> --dave
>>
>> --
>> David Collier-Brown,         | Always do right. This will gratify
>> System Programmer and Author | some people and astonish the rest
>> davecb@spamcop.net           |                      -- Mark Twain
>>
>> _______________________________________________
>> Bloat mailing list
>> Bloat@lists.bufferbloat.net
>> https://lists.bufferbloat.net/listinfo/bloat
>
>
-- 
David Collier-Brown,         | Always do right. This will gratify
System Programmer and Author | some people and astonish the rest
davecb@spamcop.net           |                      -- Mark Twain


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  reply	other threads:[~2018-11-28 20:34 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-28 16:32 Bruno George Moraes
2018-11-28 16:55 ` Dave Taht
2018-11-28 18:25   ` Dave Collier-Brown
2018-11-28 18:26   ` David Collier-Brown
2018-11-28 19:02     ` Dave Taht
2018-11-28 20:34       ` David Collier-Brown [this message]
2018-11-29  2:33   ` Dave Taht
  -- strict thread matches above, loose matches on Subject: below --
2018-11-24 23:29 Dave Taht
2018-11-25  6:44 ` Mikael Abrahamsson

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