From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from sonic304-25.consmr.mail.ne1.yahoo.com (sonic304-25.consmr.mail.ne1.yahoo.com [66.163.191.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 43BAF3B2A4 for ; Wed, 28 Nov 2018 15:34:58 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rogers.com; s=s2048; t=1543437296; bh=G728sUaaLIGTmZntNIITFRAFoG0fz2jHHxuq/2zYiC8=; h=Reply-To:Subject:To:Cc:References:From:Date:In-Reply-To:From:Subject; b=Brv+mB7tkKjaq4CGs2QbPskWeL6ayKE/0bgRuIlGcYgR4MDPbbAz3YUpHBIKCpT3oJVB+qvaeAPdKfICviBL1rs0yr1dcC8nZDX6xnG4ZeoyW8LpIABiqUE0jyt1l2g0SguswG7BGzi0AhEz0MUt8mDxMJ8XVkFHgJV4SSNKjBsep0RaJl+s54NFhXHk2astAwzY2w3wD+RF9clRB19I0WLxJJbIXH/xp0HXHZA5xtRy7PDbI4vSGUPRpx2Q0DmXA7qr7d4p5irF3tdqdJEW7khWVAUhDk95A0Ya0W+JdV45omE4oJm1H02WVRXEg1jDHwQCV8c5oiJxjKB8nrpb1w== X-YMail-OSG: kSK06wUVM1lY9X19EJvuY1JpH3EWFCkKu9eWbn9EGxXzQxFVJeALGPjqFWLug.E av3Jg165Da84mWq3YpNak7kM3pKRGLI2l49nJHEwWuUh2clPt4GjEyr3SCGE9ap2CV6okQOLZygC KPjXKTPplpObi5AsrarkhOVp0eKDSqQREZaveeLzPKG5zOKMSjNSzchJPceej7tuhqVQTCr62Nmm h1BxbUT5vOvBf0hzGzDTmpTGmK8.Y81w4rpOGPZRGOuZhGCSrqDpTbkB.l2KnJbOyLvr.dumW8dj MU3Vh41bdYHbwPAMpwjUQ_vuLIMJOTsneZGBMIfIKgA6Y4pK2I3RD9eRqeQFAdtutRmec8q7voIT PeEGsZOJSSu7P4BQ9pXooyHJ8sGszEJMJv_y2oorsu4ZsK0Ww1kWweX1BimTVvOHJtYFUT7q_CKM S3oLAcTudQobZUoXCWutofVtS2S1LcOjrPmjEDcT9ArIIpvqS4jGuaoZk.p8Oc1p85wEMFCeBFJ6 ntLK6HfQs_hXF1gMi88bn0IrjqrSwO9nHeHh0etzIX_L58qxsRdkUrie_wqPGCO3S9xTx.u0mrSq FVGRdJgcjC3QI5Jx8mEa5wTojReyDKFgKt7GF2ZhdAsAIRwSVIPalgSJp52LxCsMNVZG3kOQXlAF U9weiqPoP5i_28AFgSD7fhLlWhurmJmLqzls3LdvoMN6MmxcUYkhMMDKA3p6TGARqn6cI8rP1Y3V ocUxMOUzCZgUjb15gQ6l5aIpIW7RsFlrVHFaG.tQOKGiwHTf2ySZRPcB9kEBQFb.4_5FanvMot_w Jnfq2QwydW.KuQJExnkBxXWPvj0rMlp9vNToH6sQ29oLZbN6kWBJypWybnHM2Ev_B83YVdJymUrJ 3gHTsVrhebqOARqBtQ04feT7HALygObef.dDnzGo_vu5ZTjgxP7fsZrYxNXxzfXkItRTetKXzIJl Ikm7Epw1iHqVqq8CEqgII497ZtbZWaIqKR3LnNu2XiGhP7nQ3XLfhzbFZ_1YgpR8rJzIGjPj_gGa 8fmb_6pUnsKO2.J8pJqo_Wvi8B6VX11tFXhxSiWTdJKK_rqeouF1HC.JHaA_5Jg4au8fjQqwqP7Z 0n04OuAUDrjx0AIzUQzR.Q8awuJ6OPQ-- Received: from sonic.gate.mail.ne1.yahoo.com by sonic304.consmr.mail.ne1.yahoo.com with HTTP; Wed, 28 Nov 2018 20:34:56 +0000 Received: from CPEbc4dfba21363-CMbc4dfba21360.cpe.net.cable.rogers.com (EHLO [192.168.0.15]) ([99.242.215.211]) by smtp421.mail.ne1.yahoo.com (Oath Hermes SMTP Server) with ESMTPA ID 4d407349ccdd6c2f4bac70bf68ccad49; Wed, 28 Nov 2018 20:34:54 +0000 (UTC) Reply-To: davecb@spamcop.net To: Dave Taht , David Collier-Brown Cc: bloat References: <87y39dywei.fsf@taht.net> <10f64620-5b45-5c84-e468-044cc32fb92e@rogers.com> From: David Collier-Brown Message-ID: <7b414124-fdd1-e9c7-9c6f-a66049ddcd56@rogers.com> Date: Wed, 28 Nov 2018 15:34:53 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------21F179BD1DC1EC6E289EC288" Content-Language: en-US Subject: Re: [Bloat] known buffer sizes on switches X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 20:34:58 -0000 This is a multi-part message in MIME format. --------------21F179BD1DC1EC6E289EC288 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit That would be really cool: I loved the Mips we had at YorkU.ca --dave On 2018-11-28 2:02 p.m., Dave Taht wrote: > I really don't know a whole heck of a lot about where mips is going. > Certainly they remain strong in the embedded market (I do like the > edgerouter X a lot), but as for their current direction or future > product lines, not a clue. > > I used to know someone over there, maybe he's restored new directions. > Last I recall he was busy obsoleting a whole lot of instruction space > in order to make room for "new stuff". He'd even asked me if adding an > invsqrt to the instruction set would help, and I sadly replied that > that bit of codel was totally invisible on a trace..... > > I really like(d) mips. ton of registers, better instruction set than > arm (IMHO), no foolish processor extensions. > > On Wed, Nov 28, 2018 at 10:26 AM David Collier-Brown wrote: >> On 2018-11-28 11:55 a.m., Dave Taht wrote: >> >>> Thank you for that. I do have a long standing dream of a single chip >>> wifi router, with the lowest SNR possible, and the minimum number of >>> pins coming off of it. I'd settle for 32MB of (static?) ram on chip as >>> that has proven sufficient to date to drive 802.11n.... >>> >>> which would let you get rid of both the L2 and L1 cache. That said, I >>> think the cost of 32MB of on-chip static ram remains a bit high, and >>> plugging it into a mips cpu, kind of silly. Someday there will be a case >>> to just doing everything on a single chip, but... >> I could see 32MB or more of fast memory on-chip as being attractive when >> one is fighting with diminishing returns in CPU speed and program >> parallelizability. >> >> In the past that might have excited MIPS, but these days less so. Maybe >> ARM? IBM? >> >> --dave >> >> -- >> David Collier-Brown, | Always do right. This will gratify >> System Programmer and Author | some people and astonish the rest >> davecb@spamcop.net | -- Mark Twain >> >> _______________________________________________ >> Bloat mailing list >> Bloat@lists.bufferbloat.net >> https://lists.bufferbloat.net/listinfo/bloat > > -- David Collier-Brown, | Always do right. This will gratify System Programmer and Author | some people and astonish the rest davecb@spamcop.net | -- Mark Twain --------------21F179BD1DC1EC6E289EC288 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 7bit

That would be really cool: I loved the Mips we had at YorkU.ca

--dave

On 2018-11-28 2:02 p.m., Dave Taht wrote:
I really don't know a whole heck of a lot about where mips is going.
Certainly they remain strong in the embedded market (I do like the
edgerouter X a lot), but as for their current direction or future
product lines, not a clue.

I used to know someone over there, maybe he's restored new directions.
Last I recall he was busy obsoleting a whole lot of instruction space
in order to make room for "new stuff". He'd even asked me if adding an
invsqrt to the instruction set would help, and I sadly replied that
that bit of codel was totally invisible on a trace.....

I really like(d) mips. ton of registers, better instruction set than
arm (IMHO), no foolish processor extensions.

On Wed, Nov 28, 2018 at 10:26 AM David Collier-Brown <davec-b@rogers.com> wrote:

On 2018-11-28 11:55 a.m., Dave Taht wrote:


Thank you for that. I do have a long standing dream of a single chip
wifi router, with the lowest SNR possible, and the minimum number of
pins coming off of it. I'd settle for 32MB of (static?) ram on chip as
that has proven sufficient to date to drive 802.11n....

which would let you get rid of both the L2 and L1 cache. That said, I
think the cost of 32MB of on-chip static ram remains a bit high, and
plugging it into a mips cpu, kind of silly. Someday there will be a case
to just doing everything on a single chip, but...

I could see 32MB or more of fast memory on-chip as being attractive when
one is fighting with diminishing returns in CPU speed and program
parallelizability.

In the past that might have excited MIPS, but these days less so. Maybe
ARM? IBM?

--dave

--
David Collier-Brown,         | Always do right. This will gratify
System Programmer and Author | some people and astonish the rest
davecb@spamcop.net           |                      -- Mark Twain

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-- 
David Collier-Brown,         | Always do right. This will gratify
System Programmer and Author | some people and astonish the rest
davecb@spamcop.net           |                      -- Mark Twain
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