Re: [Bloat] known buffer sizes on switches

[Dave Taht <dave@taht.net>]

Bruno George Moraes <brunogm0@gmail.com> writes:

>     Nice resource, thanks.
>
> If someone wonders why things look the way they do, so it's all about 
> on-die and off-die memory. Either you use off-die or on-die memory, often 
> SRAM which requires 6 gates per bit. So spending half a billion gates 
> gives you ~10MB buffer on-die. If you're doing off-die memory (DRAM or 
> similar) then you'll get the gigabytes of memory seen in some equipment. 
> There basically is nothing in between. As soon as you go off-die you might 
> as well put at least 2-6 GB in there.
>
> There are some reasearch on new memory devices with unexpected
> results...
> https://ieeexplore.ieee.org/document/8533260
>
>     The HMC memory allows improvements in execution time and consumed
>     energy. In some situations, this memory type permits removing the
>     L2 cache from the memory hierarchy. 
>
> HMC parts start at 2GB 

Thank you for that. I do have a long standing dream of a single chip
wifi router, with the lowest SNR possible, and the minimum number of
pins coming off of it. I'd settle for 32MB of (static?) ram on chip as
that has proven sufficient to date to drive 802.11n....

which would let you get rid of both the L2 and L1 cache. That said, I
think the cost of 32MB of on-chip static ram remains a bit high, and
plugging it into a mips cpu, kind of silly. Someday there will be a case
to just doing everything on a single chip, but...

>
>
> _______________________________________________
> Bloat mailing list
> Bloat@lists.bufferbloat.net
> https://lists.bufferbloat.net/listinfo/bloat