From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.taht.net (mail.taht.net [IPv6:2a01:7e00::f03c:91ff:feae:7028]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 6F2813B2A4 for ; Wed, 28 Nov 2018 11:55:30 -0500 (EST) Received: from dancer.taht.net (unknown [IPv6:2603:3024:1536:86f0:eea8:6bff:fefe:9a2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.taht.net (Postfix) with ESMTPSA id 20F3C221E9; Wed, 28 Nov 2018 16:55:28 +0000 (UTC) From: Dave Taht To: Bruno George Moraes Cc: Bufferbloat lists bloat References: Date: Wed, 28 Nov 2018 08:55:17 -0800 In-Reply-To: (Bruno George Moraes's message of "Wed, 28 Nov 2018 14:32:10 -0200") Message-ID: <87y39dywei.fsf@taht.net> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Subject: Re: [Bloat] known buffer sizes on switches X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 16:55:30 -0000 Bruno George Moraes writes: > Nice resource, thanks. > > If someone wonders why things look the way they do, so it's all about > on-die and off-die memory. Either you use off-die or on-die memory, often > SRAM which requires 6 gates per bit. So spending half a billion gates > gives you ~10MB buffer on-die. If you're doing off-die memory (DRAM or > similar) then you'll get the gigabytes of memory seen in some equipment. > There basically is nothing in between. As soon as you go off-die you might > as well put at least 2-6 GB in there. > > There are some reasearch on new memory devices with unexpected > results... > https://ieeexplore.ieee.org/document/8533260 > > The HMC memory allows improvements in execution time and consumed > energy. In some situations, this memory type permits removing the > L2 cache from the memory hierarchy. > > HMC parts start at 2GB Thank you for that. I do have a long standing dream of a single chip wifi router, with the lowest SNR possible, and the minimum number of pins coming off of it. I'd settle for 32MB of (static?) ram on chip as that has proven sufficient to date to drive 802.11n.... which would let you get rid of both the L2 and L1 cache. That said, I think the cost of 32MB of on-chip static ram remains a bit high, and plugging it into a mips cpu, kind of silly. Someday there will be a case to just doing everything on a single chip, but... > > > _______________________________________________ > Bloat mailing list > Bloat@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/bloat