From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 0CC923B2A4 for ; Wed, 28 Nov 2018 21:33:51 -0500 (EST) Received: by mail-qk1-x72a.google.com with SMTP id q70so232844qkh.6 for ; Wed, 28 Nov 2018 18:33:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=SaI+7hr7hmvej+p1WKtDHD4Dp/kV7QaiL49o1dwkTRo=; b=Cbl8WRyPm+snGhnlVmHaPNjCFmA9fReppzYzG3E4GTb/6iOgJq71nzyxU+8ZZZ6LrF 1rSzanN1wvjgut3OeCAMUTYV3HGY9KtGC7tlZyr7PfbsEgWVHbeUHdc0TWmctAj3y3ey 36gpBj7DLSF4rsDPlUx3F117vHqealq/8myI+3YdnsTTgIKwNlTtI8FhfIeqmhvQ0MRR PKpQ4HiqtksNUog6lPpHSLUmTxZ/JVGxhv1cyJ0RyJsNgQhsUjyjYgkK2FYv1UqSe1H5 2Uls9TNZuTkHbRAE1eOaP9ptDxiciycipjPEkW3hA3dPJRlRHZSqXVh/Q8L5HpuXeoTw ndSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=SaI+7hr7hmvej+p1WKtDHD4Dp/kV7QaiL49o1dwkTRo=; b=FY2X2WWAEzBzJZy6ZxNh1Gvk94D7VeRhxxG2/lMkifcHlVTmWsH//l3H5Dg+u/sZzW 42d7RvCicU0AJ2MDhAmxywqeF132F4MfVi9k0B7PpuI75kS2nkqSuhoI7295lqPcV3N+ ZB5ft7Mo9bGZKDQw6++rZx+oj5a4Hr7ccYGeSllJZWEQ2p5YftKppz0sAfldAsWDcbqz t50RZmFO97u5ddKUx1wpzJrXy8UIPbevEbOAK12uE2gymqOg1N1XYukS9KuVKmYXjHzh t7qr+A94nNGzzt3pZBaHrcPT2Pia3tbk0r4xWSv6DTQYGIPjn6x2wUXfd6XMm9+Nrb7S hDLg== X-Gm-Message-State: AA+aEWbmxiQNG2uD3TnKObFyZwQ4CScLwfZff2r5J4IjH+zUYORvflwo rmCGiAEeOEirW7GFVBcX6VfgIG91SUsSfrXKYRo= X-Google-Smtp-Source: AFSGD/UIkjkpUveiWn0x98z/kiiUI+xZTPihX/oWOUEtw8xVQ/DGmGRZedD1Dck/Aa8WJ9qtLVOF4xUjv0R/Ya6IStU= X-Received: by 2002:ae9:ee02:: with SMTP id i2mr35724938qkg.179.1543458830349; Wed, 28 Nov 2018 18:33:50 -0800 (PST) MIME-Version: 1.0 References: <87y39dywei.fsf@taht.net> In-Reply-To: <87y39dywei.fsf@taht.net> From: Dave Taht Date: Wed, 28 Nov 2018 18:33:38 -0800 Message-ID: To: =?UTF-8?Q?Dave_T=C3=A4ht?= Cc: Bruno George Moraes , bloat Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Bloat] known buffer sizes on switches X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Nov 2018 02:33:51 -0000 On Wed, Nov 28, 2018 at 8:55 AM Dave Taht wrote: > > Bruno George Moraes writes: > > > Nice resource, thanks. > > > > If someone wonders why things look the way they do, so it's all about > > on-die and off-die memory. Either you use off-die or on-die memory, oft= en > > SRAM which requires 6 gates per bit. So spending half a billion gates > > gives you ~10MB buffer on-die. If you're doing off-die memory (DRAM or > > similar) then you'll get the gigabytes of memory seen in some equipment= . > > There basically is nothing in between. As soon as you go off-die you mi= ght > > as well put at least 2-6 GB in there. > > > > There are some reasearch on new memory devices with unexpected > > results... > > https://ieeexplore.ieee.org/document/8533260 > > > > The HMC memory allows improvements in execution time and consumed > > energy. In some situations, this memory type permits removing the > > L2 cache from the memory hierarchy. > > > > HMC parts start at 2GB That effort actually looks pretty promising. I liked the support for atomic ops too, offloaded.There are also so many useful operations that I'd like to see offloaded to ram - like zeroing memory regions as one example. http://www.hybridmemorycube.org/ Will probably run hot. But: grump: I still don't "get" why the traditional division between memory and cpu makers hasn't collapsed yet. A package like that with a cpu *in it*, and we're done. 4GB "ought to be enough for everybody". 27? years ago, back when I was attempting to write a SF novel, I had an idea for a more efficient way to pack cores and memory together. Basically: shrink the cray 1 design down to about the size of a nickel (or dime!). The cray had that rough shape for optimum routing and cooling, but... the overall shape of the package becomes a hexagon (https://en.wikipedia.org/wiki/Hexagon) cylinder. That gives you 6 or 12 vertical flat surfaces to mount chips on (or just let them stand in slots on the package). There's one natural crossbar bus at the center, connecting the 6 "core" chips more rapidly than the edges. Top, bottom and sides of the package can be used for I/O, power and so on, and each hexagonal component wedged tightly together (instead of today's north-south east-west architectures you get 2 more dimensions horizontally) fill the package with some sort of coolant. Seal it up tight. Test the module as a whole and ship 'em in palletloads. I'm pretty sure the heat circulates from the center out naturally, in every orientation, but what the heck, stick in some MEMs fans in there to keep things pumping along. that design naturally led to 2 cpu chips and 4 memories. Or 4 cpu chips and 2 memories. or 2 cpus 2 mems and 2 IOs. Before you started coming up with things to do with the outer 6 sides. I I never thought separating ram from cpu by more than a millimeter was a good idea..... It's a quite a jump to envision going from the cray-1 (115kw!!!) down to the size of a nickel! But everybody has a cray-1 now. They just run too hot. And are often not suited to task, just like the cray was. https://en.wikipedia.org/wiki/Cray-1 Don't know if anyone's ever tried to pattern any circuits on a cylinder tho= ugh! We are certainly seeing a lot of multi-package modules now (like in epyc) but I'd like 'em to be taller and not need so many darn pins. A full blown wifi router on chip wouldn't need more than... oh... this many pins: https://www.amazon.com/Makerfocus-ESP8266-Wireless-Transceiver-Compatible/d= p/B01EA3UJJ4/ref=3Dasc_df_B01EA3UJJ4/?tag=3Dhyprod-20&linkCode=3Ddf0&hvadid= =3D309773039951&hvpos=3D1o1&hvnetw=3Dg&hvrand=3D15072864816819105911&hvpone= =3D&hvptwo=3D&hvqmt=3D&hvdev=3Dc&hvdvcmdl=3D&hvlocint=3D&hvlocphy=3D9032156= &hvtargid=3Dpla-599566692924&psc=3D1 > Thank you for that. I do have a long standing dream of a single chip > wifi router, with the lowest SNR possible, and the minimum number of > pins coming off of it. I'd settle for 32MB of (static?) ram on chip as > that has proven sufficient to date to drive 802.11n.... > > which would let you get rid of both the L2 and L1 cache. That said, I > think the cost of 32MB of on-chip static ram remains a bit high, and > plugging it into a mips cpu, kind of silly. Someday there will be a case > to just doing everything on a single chip, but... > > > > > > > _______________________________________________ > > Bloat mailing list > > Bloat@lists.bufferbloat.net > > https://lists.bufferbloat.net/listinfo/bloat > _______________________________________________ > Bloat mailing list > Bloat@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/bloat --=20 Dave T=C3=A4ht CTO, TekLibre, LLC http://www.teklibre.com Tel: 1-831-205-9740