From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 066963BA8E for ; Tue, 27 Nov 2018 14:09:57 -0500 (EST) Received: by mail-qk1-x734.google.com with SMTP id q70so15283828qkh.6 for ; Tue, 27 Nov 2018 11:09:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=sUAB+AWHodJOiYTZap4MJVRliUdr3SkL/cKiTdUco2E=; b=nejIdJA8LX1kQGIqhNeQBX3RLw1ngDOJWA5fhzjCXy6J5fFG6KTsTk1RaBtwcD+o2d iEwrWe1HfYOIsWX7z7aqumFMRg0n47ne+vNUZYYbUm26sU5aTvRGiFxhBNq/qaQXCdTx lZDv2uqwwvLitu1QVtJcTnECJ7wiBT/EXbDLQvoSfltJF2QG+hoCfD1tZEjwtpofmHKA QCrmMAnTYBct9EbJ+Bg0C1agEwKKVHoSIGrehA3XQ4i/2T9M84NySUDfzZXZsNdjrZKI YMSPndWO6u/kQpuX0wV21l4HBp4IpXb5DRl37exDgIruFtEogzokDjOKhuvjBUWB69a4 RZfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=sUAB+AWHodJOiYTZap4MJVRliUdr3SkL/cKiTdUco2E=; b=RZg6v8ckvlKxmWINunfUwjq2GV/cK2AkUO+GiNQHlPElsqwuwzc56lqSyVQODILuEU YMexEId16TfqnyFh1/wJ0tbRqvW+vlwJBDZY+hgXL7LmD2C/kj6fB1cAnnw9p+zVw74Q e1JeoIY8KsrLJcTJn5xHTBE7qkBe96I0ztf//2vtoG14wzHu4Ft7Yzwtluk05x6fWihJ 66SC3CR+XHr8Br/aL+lGwROQviFIJJqbxxsK5qv+YXmPrDyCieh5WNbDnNoIMasvCufh fZve3bYHqtM95fuh0ExsLFR22nMeyD8RwlpR08S6CMjBD3PE0tFa+v/kaC51BuWgGc+t pstA== X-Gm-Message-State: AA+aEWaOzN+i/rAsGjIuqMNcbRZ/Xj+E1smRHvTWXT53IDPf/YPoL8si Fu1dN5ss1rKyNxtYkDuriputRl2Q2hnJEZx+m5M= X-Google-Smtp-Source: AFSGD/XhMGiQbYKPhhuCXafaAy4PN/kTPgMX2O1LV+SKHe9QKyPGtCWZGa/Ts05WAGa4UZ4Ao3EvPnefnyTc0Aqxhy4= X-Received: by 2002:a37:18d5:: with SMTP id 82mr30230426qky.65.1543345797479; Tue, 27 Nov 2018 11:09:57 -0800 (PST) MIME-Version: 1.0 References: <6C1479A8-43E8-4F89-BCEA-1D28CA3E8589@heistp.net> <87r2fbzrng.fsf@taht.net> <4FB37CD5-0DAB-479E-8C8C-671D442D668E@akamai.com> <20181127103114.3f403d8a@xeon-e3> In-Reply-To: <20181127103114.3f403d8a@xeon-e3> From: Dave Taht Date: Tue, 27 Nov 2018 11:09:44 -0800 Message-ID: To: Stephen Hemminger Cc: jholland@akamai.com, bloat Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Bloat] one benefit of turning off shaping + fq_codel X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Nov 2018 19:09:58 -0000 On Tue, Nov 27, 2018 at 10:31 AM Stephen Hemminger wrote: > > On Tue, 27 Nov 2018 18:14:01 +0000 > "Holland, Jake" wrote: > > > On 2018-11-23, 08:33, "Dave Taht" wrote: > > Back in the day, I was a huge fan of async logic, which I first > > encountered via caltech's cpu and later the amulet. > > > > https://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU > > > > ... > > > > I've never really understood why it didn't take off, I think, in pa= rt, > > it doesn't scale to wide busses well, and that centrally clocked de= signs > > are how most engineers and fpgas and code got designed since. Anyth= ing > > with delay built into it seems hard for EEs to grasp.... but I wish= I > > knew why, or had the time to go play with circuits again at a reaso= nable > > scale. > > > > At the time, I was told the objections they got were that it uses about= 2x the space for the same functionality, and space usage is approximately = linear with the chip cost, and when under load you still need reasonable co= oling, so it was only considered maybe worthwhile for some narrow use cases= . And the pentultimate cost here was unpredictable and many power states, hyperthreading (which is looking to die post spectre), and things like ddpk which spin processors madly to keep up. I always liked things like I wish I knew more about what fulcrum did in their switch designs... everybody knows I'm a fan of the mill cpu which has lots of little optimizations close to each functional unit (among many other things using virtual memory internally for everything, and separating out the PLB (protection level buffer) from the TLB). I would really like to bring back an era where cpus could context or security level switch in 5 clocks. Someday something like that will be built. Til then, the closest chip to something I'd like to be working on for networks is how the xmos is designed: https://en.wikipedia.org/wiki/XMOS#xCORE_multicore_microcontrolle= rs - or https://www.xmos.com/developer/silicon/xcore200-ethernet which has 1MByte of single-clock sram on it. "The xCORE architecture delivers, in hardware, many of the elements that are usually seen in a real-time operating system (RTOS). This includes the task scheduler, timers, I/O operations, and channel communication. By eliminating sources of timing uncertainty (interrupts, caches, buses and other shared resources), xCORE can provide deterministic and predictable performance for many applications. A task can typically respond in nanoseconds to events such as external I/O or timers. This makes it possible to program xCORE devices to perform hard real-time tasks that would otherwise require dedicated hardware." Nobody else's ethernet controllers work this way. > > > > I don't really know enough to confirm or deny the claim, and the use ca= ses may have gotten a lot closer to a good match by now, but this was the o= pinion of at least some of the people involved with the work, IIRC. > > > > > > _______________________________________________ > > Bloat mailing list > > Bloat@lists.bufferbloat.net > > https://lists.bufferbloat.net/listinfo/bloat > > With asynchronous circuits there is too much unpredictablity and instabil= ity. > Seem to remember there are even cases where two inputs arrive at once and= output is non-determistic. Yes, that was a big problem... in the 90s... but cpus *were* successfully designed that didn't do that. I am the sort of character that is totally willing to toss out decades of evolution in chip design in order to get better SNR for wireless. :) I wish I knew of a mailing list where I could get a definitive answer on "modern problems with async circuits", or an update on the kind of techniques the new AI chips were using to keep their power consumption so low. I'll keep googling. > _______________________________________________ > Bloat mailing list > Bloat@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/bloat --=20 Dave T=C3=A4ht CTO, TekLibre, LLC http://www.teklibre.com Tel: 1-831-205-9740