Re: [Bloat] [Starlink] Of interest: Comcast AQM Paper

[Jonathan Morton <chromatix99@gmail.com>]

I firmly believe this is due to an I/O bottleneck in the SoC between
the network complex and the CPU complex, not due to any limitation of
the CPU itself.  It stems from the reliance on accelerated forwarding
hardware to achieve full line-rate throughput.  Even so, I'd much
rather have 40Mbps with Cake than 400Mbps with a dumb FIFO.  (Heck,
40Mbps would be a big upgrade from what I currently have.)  I think
some of the newer Atheros chipsets are less constrained in this
respect.

There are two reasonably good solutions to this problem in the hands
of the SoC vendors:

1: Relieve that I/O bottleneck, so that the CPU can handle packets at
full line rate.  I assume this is not hugely complicated to implement,
and just requires a sufficient degree of will to select the right
option from the upstream fabless IP vendor's design library.

2: Implement good shaping, FQ, and AQM within the network complex.  At
consumer broadband/LAN speeds, this shouldn't be too difficult (unlike
doing the same at 100+ Gbps), but it does require a significant amount
of hardware design and validation, and that tends to have long lead
times.

There is a third solution in the hands of us mere mortals:

3: Leverage the Raspberry Pi ecosystem to build a CPE device that
meets our needs.  This could be a Compute Module 4 (which has the
necessary I/O throughput) mounted on a custom PCB that provides
additional Ethernet ports and some reasonable Wifi AP.  It could
alternatively be a standard Pi 4B with some USB Ethernet and Wifi
hardware plugged into it.  Either will do the job withhout any
Ethernet bottlenecks, although the capabilities of USB Wifi dongles
are usually quite limited.

 - Jonathan Morton