From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-x22b.google.com (mail-ig0-x22b.google.com [IPv6:2607:f8b0:4001:c05::22b]) by lists.bufferbloat.net (Postfix) with ESMTPS id CE92D3B2D6 for ; Tue, 5 Jan 2016 19:06:04 -0500 (EST) Received: by mail-ig0-x22b.google.com with SMTP id ik10so22283728igb.1 for ; Tue, 05 Jan 2016 16:06:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=M+6q31sdq9RGdWp7FC91Si4VwkgzWn03vsQXm1FDFAo=; b=CfsMAfzvE1nrvrCiSsdy6IzJDVAtirnqxb96EHd4SYcCGrUpf1xOA4NDTuXxEyz+A4 r56ltDe9ABxv8kfxldgnZfUOVza4lbcLjHo4vwt32U8Lfy0sJDSYwynrv/oCnvCn76Bd ByQazV3lGQjoUMpygVI/cTH1iCgwEqpAqTnZNRNKY2SH7hKZSJ0Banpv9yVlgGGiqyq0 QHn5wPjKwjUSaJdV1/qXeTmu/lw1/G4aEoiuXiv9rwG4GJNWm+3HAZCapxX+e/aYmwXp 1wQx58fSytAkdf7+KF0GmKh6OkTSnCqtnOkULDwuBWCDDu1T3o+tqB0bUs8MFYSOOmP6 2Cew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=M+6q31sdq9RGdWp7FC91Si4VwkgzWn03vsQXm1FDFAo=; b=LPBTTjGSQjrMFPyZRziDlGJdG8+ccepxZqWwaykjCuqGWNots4B3EekGb1Q1X7TJuD FJVwmVYC/b/OhTHzbPQTUa6o8OTH996WhDrgxnGtoGz4alNIQ5d4on6GwWKnfCdyORLO 43e+7lFLCxAKsv0gZ0i14z+qzzw3J5l5N6YNZ2g3bcRPnBnshmCaBeCBrrc+Rebl7q/5 AFCqe+wtGrMH+coVRvto5vUvm0dEVPIRWUgGs+N7vkQbv+E42PZQGRqmhZQmpJgTw1sw tV445nrbceqTUl+sxneoiwzU6g4avajSba75dWXGmiguhTIpe/BuQYnS1A94KlyFr5lc zJuw== X-Gm-Message-State: ALoCoQlLwN3g/kfqV05kdk5ZxNA8r0E3zRYU1z0tyK3/yTO11acdBlLo4o7M4zTwTpCgGQvCALWZ2K2N9CO+25iSkqNRRKasqQ== MIME-Version: 1.0 X-Received: by 10.50.70.38 with SMTP id j6mr6376257igu.13.1452038763354; Tue, 05 Jan 2016 16:06:03 -0800 (PST) Received: by 10.64.108.229 with HTTP; Tue, 5 Jan 2016 16:06:03 -0800 (PST) In-Reply-To: <20160106000151.GA5332@sesse.net> References: <165DB6E9-A6DD-4626-B6AA-E1B2DBA0B5FA@gmail.com> <568C1209.5050403@taht.net> <20160106000151.GA5332@sesse.net> Date: Tue, 5 Jan 2016 16:06:03 -0800 Message-ID: From: Stephen Hemminger To: "Steinar H. Gunderson" Cc: "bloat@lists.bufferbloat.net" Content-Type: multipart/alternative; boundary=047d7b41410ab0c4cf05289f1e2d Subject: Re: [Bloat] Hardware upticks X-BeenThere: bloat@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: General list for discussing Bufferbloat List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2016 00:06:05 -0000 --047d7b41410ab0c4cf05289f1e2d Content-Type: text/plain; charset=UTF-8 The expensive part is often having to save and restore all the state in registers and other bits on context switch. On Tue, Jan 5, 2016 at 4:01 PM, Steinar H. Gunderson wrote: > On Tue, Jan 05, 2016 at 03:36:10PM -0600, Benjamin Cronce wrote: > > You can't have different virtual memory space and not take some large > > switching overhead without devoting a lot of transistors to massive > caches. > > And the larger the caches, the higher the latency. > > I'm sure you already know this, but just to add to what you're saying: > Modern CPUs actually have cache-line tagging tricks so that they don't have > to blow the entire L1 just because you do a context switch. It would be too > expensive. > > /* Steinar */ > -- > Homepage: https://www.sesse.net/ > _______________________________________________ > Bloat mailing list > Bloat@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/bloat > --047d7b41410ab0c4cf05289f1e2d Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
The expensive part is often having to save and restore all= the state in registers and other bits on context switch.


On Tue, Jan 5,= 2016 at 4:01 PM, Steinar H. Gunderson <sgunderson@bigfoot.com>= ; wrote:
On Tue, = Jan 05, 2016 at 03:36:10PM -0600, Benjamin Cronce wrote:
> You can't have different virtual memory space and not take some la= rge
> switching overhead without devoting a lot of transistors to massive ca= ches.
> And the larger the caches, the higher the latency.

I'm sure you already know this, but just to add to what you'= re saying:
Modern CPUs actually have cache-line tagging tricks so that they don't = have
to blow the entire L1 just because you do a context switch. It would be too=
expensive.

/* Steinar */
--
Homepage: https://www.sesse.net/
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Bloat mailing list
Bloat@lists.bufferbloat.net<= /a>
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