From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io1-xd2c.google.com (mail-io1-xd2c.google.com [IPv6:2607:f8b0:4864:20::d2c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id C44843B2A4; Wed, 29 Sep 2021 12:22:08 -0400 (EDT) Received: by mail-io1-xd2c.google.com with SMTP id r75so3858528iod.7; Wed, 29 Sep 2021 09:22:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :content-transfer-encoding; bh=1ecySe8Kj4eyDG6/e1o/5wQ8UrC77sZ17NkHzw9Iy2c=; b=b0UAmjhOSMkOfRrfkWaacEzin7mix/s1eafpyNGTBwRJq9/mKPCvPtkyxadyDBbKvw NxxNqyRs0w/gVjxxMH3kKLDh+gQQZ+goa1iUDdBxuBJJmpM2XLy0SOFpMrNNKKT6xglO 685N6qzMBgLNhZtdm1Zg1LVowHauB0Bcn/ReLJrX9Nrya3meyZ8RpfQ1QOKDxagjCdiV vOVGlcjkJYIDJpAY+JmSos0LLXuESaLyeNCwZxpWPnJSpv/34YSLy4tuJH3vHxOJBdAh 5mtwFC6l97nMVLQAE+xqetli6amCOxFT3WDKh6T/i4FOcRQmO2RajofXhO6Q5qxCjMZH DWMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:content-transfer-encoding; bh=1ecySe8Kj4eyDG6/e1o/5wQ8UrC77sZ17NkHzw9Iy2c=; b=ueCM44BVM6nAkY53DjGusN4gQOUbKaGL/9LocMS2AJArv5OcDiOh77z5965ilYyWhd 3iLQ94yzVO0B3iF6KxRF+6jmVi7G5+RjsHZQ7iC0l62ICQiXkclzLlL5rs0Wm/7WmU0B piqZon1BFukWA9a+opYvyMKgJod6GQ8S73sfCw83JLYCUzzuuFsWKscIfeP9KQqbZ22M gxhhNnQqN07SG6v4YA9m1CFjzIsptE9PHfhZ4hTix/J3HrAGSYS/Bze1J9iXujOOjsmS edQM+GrLwK1zRyJAdklW6XbJStwhAiUK7CMFstTlrEl4OcsWEmpJo8u8SQ1ijTFjYYhH qJRQ== X-Gm-Message-State: AOAM5338nlv2DUW+7731uCI/XIL9rlBFMWbmPzHmhmbTkN4Rgb6FFbkV CKk49D3HlPAiG4iSiCfEKcpK9/Z2SE90wi+Tf217rF2a X-Google-Smtp-Source: ABdhPJynk0rGXntzmXjtnsKagdCyUUrEuqMnAixAbUCWOaNG4I3XTdC7gWfaM0Ko8RNeQ8y4yM/DKD6/K6gdtps02kQ= X-Received: by 2002:a05:6602:180e:: with SMTP id t14mr482809ioh.204.1632932527636; Wed, 29 Sep 2021 09:22:07 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Dave Taht Date: Wed, 29 Sep 2021 09:21:54 -0700 Message-ID: To: Make-Wifi-fast , Cake List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Cake] Fwd: [NetFPGA-announce] Announcing NetFPGA PLUS 1.0 X-BeenThere: cake@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Cake - FQ_codel the next generation List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Sep 2021 16:22:08 -0000 ---------- Forwarded message --------- From: Andrew Moore Date: Fri, Sep 24, 2021 at 2:58 PM Subject: [NetFPGA-announce] Announcing NetFPGA PLUS 1.0 To: It is with great excitement we announce the release of NetFPGA PLUS. NetFPGA PLUS 1.0 NetFPGA PLUS 1.0 has arrived, available in a public repository to all, links on the netfpga.org website. I=E2=80=99ve reprinted the outline, inclu= ded as part of the original announcement, at the bottom of this newsletter. The overly optimistic timetable fell to the brutal realities of the last 9 months. NetFPGA PLUS has been is a momentous effort that largely has fallen to the broad shoulders of the increasingly slim NetFPGA team at Cambridge; one person in particular deserves much credit for this huge effort and for us achieving this first release. On behalf of us all, I thank Yuta Tokusashi who has lead the NetFPGA PLUS work throughout this effort and who has managed this despite the extraordinary challenges of the last 18 months. Many critical issues were managed and overcome with the expert guidance of Noa Zilberman, while release testing and preparation would not have been possible without the assistance of Salvator Galea. This entire effort was enabled by many members of the excellent Xilinx team from Gordon Brebner=E2=80=99s leadership and enthusiasm through to the phenomenal efforts of the Open-NIC team; notably Yan Zhang, and Chris Neely, as well as critical advice from Cathal McCabe, part of Xilinx in Dublin. My personal thanks and on behalf of the NetFPGA community to each of them. (I=E2=80=99m excruciatingly aware the moment I send this email I will realise I=E2=80=99ve not credited a critical member of the team - my apolog= ies in advance.) I will leave some details to a future newsletter - in preparation - but promise it shortly, as soon as we have all caught up on our sleep. Do check out the new website, thanks to Adam Pettigrew for his efforts there; and of course do check out the public, openly available, Apache licensed, NetFPGA PLUS codebase too! Items planned for the next announcement will include 1. License change for NetFPGA 2. NetFPGA PLUS plans 3. NetFPGA SUME status Thank you all, Andrew Moore on behalf of the NetFPGA team. [direct copy of the PLUS announcement from the December 2020 NetFPGA newsle= tter] 5. Announcing NetFPGA PLUS (formerly NetFPGA 2020) - 100Gbps and beyond. At the ACM SOSR19 keynote, I announced the NetFPGA 2020 project, taking forward the NetFPGA ecosystem to 100Gbps. Called NetFPGA PLUS, this work does not require a bespoke NetFPGA board. Instead the codebase is designed to work across a number of the (commodity) Alveo boards that utilise the Xilinx UltraScale+ FPGA family. This project will provide more options for the NetFPGA community and more opportunities for NetFPGA work to continue to be the foundation stone of future education, future designs, future research, and ongoing success. At this time, we have been testing across a subset of the Xilinx Alveo board family: U200, U250, U280, and also the ancestor VCU1525 board. A typical specification (VCU1525/U200 in this case) is support for two QSFP28 100G ports, PCIe Gen3 x16 or Gen4 x8, up to 64GB of DDR4, and an FPGA which sports 2,586K system logic cells, 345Mbit of on chip memory and a great many other features beside. The U250 and U280 are even higher specification systems. Built upon the Xilinx Vivado toolchain, the initial release of the NetFPGA-PLUS system still provides the same nf_datapath architecture that we know and love. The hybrid approach of using NetFPGA and Xilinx components brings standard interfaces and board-specific blocks (e.g., CMAC, PCIe), holds promise of an easier migration between platforms, while holding constant the NetFPGA datapath and networking capabilities, alongside host software and the build, test and simulation infrastructure critical for development. In the first instance we are focussed upon those users with one or more Alveo boards in hand (or accessible remotely). The initial release (due early in the new year) will have the basic reference designs of NetFPGA-SUME: - Network Interface Card reference project - Switch reference project (simple switch and learning switch), and - IPv4 Router reference project along with the standard NetFPGA Python3 based simulation and hardware testing framework. Also on the planning list (a release for Q3 2021): - Fully integrated P4 compilation support, to provide an open P4 hardware platform - MAC/PHY support for QSFP28 to 4xSFP28, permitting up to 8 10/25Gbps ports - New generation open source network tester capable of many 100Gbps. _______________________________________________ cl-netfpga-announce mailing list cl-netfpga-announce@lists.cam.ac.uk https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-announce --=20 Fixing Starlink's Latencies: https://www.youtube.com/watch?v=3Dc9gLo6Xrwgw Dave T=C3=A4ht CEO, TekLibre, LLC