From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw0-x241.google.com (mail-yw0-x241.google.com [IPv6:2607:f8b0:4002:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id AB7793B2A4 for ; Sun, 3 Dec 2017 19:35:20 -0500 (EST) Received: by mail-yw0-x241.google.com with SMTP id m129so6061801ywb.11 for ; Sun, 03 Dec 2017 16:35:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aenertia.net; s=dkimaenertianet; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=YhymJQOdA7YDcQ5SBXGs/mjVTY9O6YT/bNP5ySOptPk=; b=JDajSqMjEus42wAPtsxj6qeOLAFRPwIFNE7Hl7+2e8qwACUvz/WkYBFgG292dpSzLh AN/EQMB+pQJKfIjja9tAOTJ48bAyydTP2najIvXyiruVdlvzWWUkHE6EBZhw9Gc12ZjC gqf6kxc/kLevSo+YIUGiw/344oGhm5AoHlf98= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=YhymJQOdA7YDcQ5SBXGs/mjVTY9O6YT/bNP5ySOptPk=; b=b58cOTUgHHJtcCC8HK9AD6eMZOrltjwQHP1yTl1nmdHVrbv4krAfYFHV6oou0GAVVm T7QMVwBHwjLDHx+OXLF05SJHsBBkNoxGn4si1YUdn10sitxW3qx2VotHnP3dsDuXHQ1k iPsPFa9rnCIe43QG6pGulKqHqYabZSgbLJ1IkIj6ehqoi6J3fXl9qKGMnaoFyTXEvzcw H6w+ZSS5kcs6z9EE7ES/3rYlF0N4CMC+7HgHNBwCUXyeXLA9L8h+Q+XSKflJ403RpGTz PO5pE2KLm3hoKYhB6G9fyzZS0y1zuJEpkrZkZRs9VMgYkYqtM6JFDmSRFiNvLZGJ4g6D Vdtg== X-Gm-Message-State: AJaThX6IhCJlYH4j5H4MfHhKru0OVkEdXWHA8K9jNwiwpn/lM2tBwaFr Rh1CvwZMMphYeZeQzE6nox/pCoTIEnQjy7nq3tZHPA== X-Google-Smtp-Source: AGs4zMagJX5nSHPCro7G64ySyc/ngffhDSB4H6QGBVh2qYJTevab+SnkzHWU9lzBG/UcvSvDuv0XRmt5Wl2FwXuozxs= X-Received: by 10.129.148.193 with SMTP id l184mr8866355ywg.454.1512347720101; Sun, 03 Dec 2017 16:35:20 -0800 (PST) MIME-Version: 1.0 Sender: aenertia@aenertia.net Received: by 10.37.173.2 with HTTP; Sun, 3 Dec 2017 16:34:59 -0800 (PST) In-Reply-To: <23960.1512346289@obiwan.sandelman.ca> References: <23960.1512346289@obiwan.sandelman.ca> From: =?UTF-8?Q?Joel_Wir=C4=81mu_Pauling?= Date: Mon, 4 Dec 2017 13:34:59 +1300 X-Google-Sender-Auth: KHeZ_lHQas58IlsIwk3TxTgI-gs Message-ID: To: Michael Richardson Cc: Dave Taht , Cake List , "cerowrt-devel@lists.bufferbloat.net" Content-Type: text/plain; charset="UTF-8" Subject: Re: [Cake] [Cerowrt-devel] quad core arm X-BeenThere: cake@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Cake - FQ_codel the next generation List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Dec 2017 00:35:20 -0000 On 4 December 2017 at 13:11, Michael Richardson wrote: > > Dave Taht wrote: . > > > On the really high end the 48 core arm boxes from cavium look interesting. > > I'm told that there is some special sauce to get them to go at the speeds the > specs say. Basically you run Linux on one core, and a special (binary blob) > micro kernel on the other 47, and manage them via FORCES. > Can confrim; we included a Cavium GPC in our Original VSG7850 as a Linux Environment along side the Trident2+ chipset. It was a nightmare just getting the NDK signed to get access to the Cavium build chain, and then it was using an ancient 2.6 kernel with Secret sauce patches.