From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-xc2b.google.com (mail-yw1-xc2b.google.com [IPv6:2607:f8b0:4864:20::c2b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id A34393BA8E for ; Fri, 3 Aug 2018 18:56:09 -0400 (EDT) Received: by mail-yw1-xc2b.google.com with SMTP id z143-v6so1567598ywa.7 for ; Fri, 03 Aug 2018 15:56:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aenertia.net; s=dkimaenertianet; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=OLDl5EKbUgS/oIkGwylu2NjKZmZmj+72pe1CZJ1n/UY=; b=a8Kq4K9S/ex9L1hZ6awLCpt/dajx7xfU2Bu0XSBPKfFAmjLKywlJ4sefUTdsImkah3 LbwGQY7ZX1zzELoI/bjFALnC+QmXmkA+Q8/v15PFbAB6aiq5ZZGpHBPO6v4l9LkDZ/Io 6wEz/dlYYFqEZw4FbtwxEecnhh/YVlkaVJDXo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=OLDl5EKbUgS/oIkGwylu2NjKZmZmj+72pe1CZJ1n/UY=; b=BsbOYwCCsuF11ue9mBOX8r5hiWpO8XUqsgqcld8mbItkVhcFSs6l0dAPN0rYdH1V+p CKyG+2XU6/xF0rLzf8RA4UK8ATIjhzxaJ+lofJNUmpFlvkn9eQ9Ifbhi7xx6Dg7a/pis 6ZiEMhp7PFAejZA2DC4aKkpyJzH/pmlUoZbUfiUuYF5RhmbcPMhzHhrlf7cWAMHviAtP A0HnkbBNmDUtJCi/31wWzZRkp+uY8UPcNU5xNqyvpXljisVMq28+W1rntJHnfbFt+5Kj meqrhS+p689K1rt1M52mjFI+FFV2tRfoALJjQIP717gjT+S11QVKEZthlrW+W8gg2S1x vKLw== X-Gm-Message-State: AOUpUlF+GG3/VwwTN0GYZtHD2jpt9RSReTAvbHLKZGKCLKhzq0S4valN mrEHfOrDoxt67e5qJPMqkBLyMCUZ6HpEUWQcJuu2Xw== X-Google-Smtp-Source: AAOMgpdD+8rOgGjRlWI/r4H8YTD3bWJ6pwNEpK6QejLoHpX/P9VaupuliY4wu/GXWMC5oqmPMUqL3i3aNdJcJP72wU4= X-Received: by 2002:a81:1201:: with SMTP id 1-v6mr3174202yws.309.1533336969020; Fri, 03 Aug 2018 15:56:09 -0700 (PDT) MIME-Version: 1.0 Sender: aenertia@aenertia.net Received: by 2002:a25:9785:0:0:0:0:0 with HTTP; Fri, 3 Aug 2018 15:55:48 -0700 (PDT) In-Reply-To: <1533310228.44199851@apps.rackspace.com> References: <1533310228.44199851@apps.rackspace.com> From: =?UTF-8?Q?Joel_Wir=C4=81mu_Pauling?= Date: Sat, 4 Aug 2018 10:55:48 +1200 X-Google-Sender-Auth: BSDoEmpfucBoHbTtPo7mk1RJ3qI Message-ID: To: "dpreed@deepplum.com" Cc: Dave Taht , Cake List , cerowrt-devel@lists.bufferbloat.net Content-Type: multipart/alternative; boundary="0000000000005c297905728fd551" Subject: Re: [Cake] [Cerowrt-devel] expressobin X-BeenThere: cake@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Cake - FQ_codel the next generation List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Aug 2018 22:56:09 -0000 --0000000000005c297905728fd551 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Needs 802.3bz capable Copper ports IMNSHO. I don't plan on buying new dev boards from until there is something with these that isn't terrible. On 4 August 2018 at 03:30, dpreed@deepplum.com wrote: > https://www.cnx-software.com/2018/08/03/clearfog-gt-8k- > high-end-networking-sbc-marvell-armada-a8040-processor/ > > Looks interesting... I like the SFP+ being there, too. > > (Regarding Xilinx ... My focus is on the FPGA. The ARM cores are less > interesting, other than that the FPGA side can directly access their cach= e > system creating a powerful, fast, coherent autonomous DDR backed memory > addressable memeory for packets that does not need processor intervention= . > But Xilinx parts are not cheap) > > > > > -----Original Message----- > From: "Dave Taht" > Sent: Wed, Aug 1, 2018 at 4:06 pm > To: dpreed@deepplum.com > Cc: "Toke H=C3=83=C2=B8iland-J=C3=83=C2=B8rgensen" , "Danie= l Ezell" < > dezell@stonescry.com>, "Cake List" , > cerowrt-devel@lists.bufferbloat.net > Subject: Re: Re: [Cerowrt-devel] expressobin > > On Wed, Aug 1, 2018 at 5:49 AM dpreed@deepplum.com wrote: > > > > Yeah. Small FF 2 port Celeron board is what I use. And I have a 4 port > Atom that runs like a bat out of hell. > > > > Currenty fiddling with Xilinx Dev boards, just put packet processing in > FPGA for Cake, and no problem with 2.5 - 10 Gb/sec. Just need a free piec= e > of low level SFP+ interfacing logic. > > cool. which? ultrascale? > > I was looking over > http://cseweb.ucsd.edu/~ssradhak/Papers/senic-nsdi14.pdf again > > > My use case is using the open ChipLink/TileLink bus from RISCV rather > than PCIe, making something that might be an open source ASIC design. > > How fast can that cpu context switch? > > > > > > > -----Original Message----- > > From: "Toke H=C3=83=C6=92=C3=82=C2=B8iland-J=C3=83=C6=92=C3=82=C2=B8rge= nsen" > > Sent: Wed, Aug 1, 2018 at 5:23 am > > To: "Dave Taht" , "Daniel Ezell" > > Cc: "Dave Taht" , "Daniel Ezell" , "Cake List" , cerowrt-devel@lists. > bufferbloat.net > > Subject: Re: [Cerowrt-devel] expressobin > > > > Dave Taht writes: > > > > > It turns out it's just two ethernets with one, connected to a 2 port > > > switch. Not what I wanted. I'd wanted something different from the > > > apu2 or edgerouter X to play with, and I know the mvneta driver was > > > bql'd. > > > > I bought one of these to play with: > > https://teklager.se/en/products/routers/tlsense-i3-4lan > > > > x86 (i3 processor), four real ethernet ports, and passively cooled. A > > bit pricy, though; more than $400... But doubles well as a combined > > switch and media player :) > > > > -Toke > > _______________________________________________ > > Cerowrt-devel mailing list > > Cerowrt-devel@lists.bufferbloat.net > > https://lists.bufferbloat.net/listinfo/cerowrt-devel > > > > > > > -- > > Dave T=C3=83=C2=A4ht > CEO, TekLibre, LLC > http://www.teklibre.com > Tel: 1-669-226-2619 > > > _______________________________________________ > Cerowrt-devel mailing list > Cerowrt-devel@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/cerowrt-devel > --0000000000005c297905728fd551 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Needs 802.3bz capable Copper ports IMNSHO.

I don't pla= n on buying new dev boards from until there is something with these that is= n't terrible.

On 4 August 2018 at 03:30, dpreed@deepplum.com <dpreed@deepplum.com> wrot= e:
https://www.cnx-software.com= /2018/08/03/clearfog-gt-8k-high-end-networking-sbc-marvell-a= rmada-a8040-processor/

Looks interesting... I like the SFP+ being there, too.

(Regarding Xilinx ... My focus is on the FPGA. The ARM cores are less inter= esting, other than that the FPGA side can directly access their cache syste= m creating a powerful, fast, coherent autonomous DDR backed memory addressa= ble memeory for packets that does not need processor intervention. But Xili= nx parts are not cheap)




-----Original Message-----
From: "Dave Taht" <dave= .taht@gmail.com>
Sent: Wed, Aug 1, 2018 at 4:06 pm
To: dpreed@deepplum.com
Cc: "Toke H=C3=83=C2=B8iland-J=C3=83=C2=B8rgensen" <toke@toke.dk>, "Daniel Ezell" <dezell@stonescry.com>, "C= ake List" <cake@lists= .bufferbloat.net>, cerowrt-devel@lists.bufferbloat.net
Subject: Re: Re: [Cerowrt-devel] expressobin

On Wed, Aug 1, 2018 at 5:49 AM dpree= d@deepplum.com=C2=A0 wrote:
>
> Yeah. Small FF 2 port Celeron board is what I use. And I have a 4 port= Atom that runs like a bat out of hell.
>
> Currenty fiddling with Xilinx Dev boards, just put packet processing i= n FPGA for Cake, and no problem with 2.5 - 10 Gb/sec. Just need a free piec= e of low level SFP+ interfacing logic.

cool. which? ultrascale?

I was looking over
http://cseweb.ucsd.edu/~ssradhak/Papers= /senic-nsdi14.pdf again

> My use case is using the open ChipLink/TileLink bus from RISCV rather = than PCIe, making something that might be an open source ASIC design.

How fast can that cpu context switch?

>
>
> -----Original Message-----
> From: "Toke H=C3=83=C6=92=C3=82=C2=B8ilan= d-J=C3=83=C6=92=C3=82=C2=B8rgensen"
> Sent: Wed, Aug 1, 2018 at 5:23 am
> To: "Dave Taht" , "Daniel Ezell= "
> Cc: "Dave Taht" , "Daniel Ezell" , "Cake List= " , cerowrt-dev= el@lists.bufferbloat.net
> Subject: Re: [Cerowrt-devel] expressobin
>
> Dave Taht=C2=A0 writes:
>
> > It turns out it's just two ethernets with one, connected to a= 2 port
> > switch. Not what I wanted. I'd wanted something different fro= m the
> > apu2 or edgerouter X to play with, and I know the mvneta driver w= as
> > bql'd.
>
> I bought one of these to play with:
> https://teklager.se/en/products/rou= ters/tlsense-i3-4lan
>
> x86 (i3 processor), four real ethernet ports, and passively cooled. A<= br> > bit pricy, though; more than $400... But doubles well as a combined > switch and media player :)
>
> -Toke
> _______________________________________________
> Cerowrt-devel mailing list
> Cerowrt-devel@l= ists.bufferbloat.net
> https://lists.bufferbloat.net/listin= fo/cerowrt-devel
>
>


--

Dave T=C3=83=C2=A4ht
CEO, TekLibre, LLC
ht= tp://www.teklibre.com
Tel: 1-669-226-2619


_______________________________________________
Cerowrt-devel mailing list
Cerowrt-devel@lists.= bufferbloat.net
https://lists.bufferbloat.net/listinfo/cero= wrt-devel

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