where the tx and rx rings are cleaned up in the same thread and there
is only one interrupt line for both.
51: 18 59244 253350 314273 PCI-MSI
1572865-edge enp3s0-TxRx-0
52: 5 484274 141746 197260 PCI-MSI
1572866-edge enp3s0-TxRx-1
53: 9 152225 29943 436749 PCI-MSI
1572867-edge enp3s0-TxRx-2
54: 22 54327 299670 360356 PCI-MSI
1572868-edge enp3s0-TxRx-3
56: 525343 513165 2355680 525593 PCI-MSI
2097152-edge ath10k_pci
and the ath10k only uses one interrupt. Maybe I'm wrong on my
assumptions, I'd think in today's multi-core environment that
processing tx and rx separately might be a win. (?)