From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk0-x234.google.com (mail-vk0-x234.google.com [IPv6:2607:f8b0:400c:c05::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id EBEE33B25E; Wed, 27 Apr 2016 18:40:19 -0400 (EDT) Received: by mail-vk0-x234.google.com with SMTP id m188so11456030vka.1; Wed, 27 Apr 2016 15:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc; bh=wiF/poJF+b31msatpf+dnUAWxIRSiBmXrBWSCl9+LcY=; b=dSEpdaJ4dPQBqnJsBp4ocdfp4cYFgcLWWCozeiL2NLEDD9jJCkasKsYb9RoSoHC/aK s+0rj9izziD+SwsJUq3xTOYn/lRC+J2Lc4T4pGqsnGdWug/1NwFFRkI7/v+NNkZO0B48 aHQ39b+26LBQA/lsehXQuG7F+o16A0tpLypvz9z5JrqFD/j0K9fwxPt+6+qpx1s25m/X KLYAEFmHoqxUz4jXiQhfdbvM6kLKv7YeakAw+WHeQp/0iz2JdKjYb5mhm+x5e9gZzCFs yFN9cqa+2ZXr+OCjjuuvOGK2QccHGAICnFolAi5E0icJxXMofXyQUtwzm/R1nKlOB73d Kx+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc; bh=wiF/poJF+b31msatpf+dnUAWxIRSiBmXrBWSCl9+LcY=; b=VVA6TEGJbDmA+/z9Ax+nxIDe+ojJt5Jz4mLAH/mAEjS3MHsFgHFSikslGeeQTmwA9J Vpg6GLtaaY+NF4YkdtyE00YSxqYztPvPY5HP1RLAEEFjkCPZJm9nmnnw0pY1ZHBEMJR1 uVqtcLK/hj6/be9ARW86oJwI1ab68vzN77GxTHY9CVhuC3wthn59d4FsUPnGm0q+7KYD WegeYxazrk49S8uByD6AzXJwr18fmKPLz6k0JM7lbbmC03qDLRV5FgwbwcqEV6fjvoh+ 5mrMmLHjH4XDmDsXZS5Fe4P06uvpDFoecQBgniJk+eJklJjFx6rrPsl+pvN2ZBGKkbwA 6YRg== X-Gm-Message-State: AOPr4FUWIwQyu7ZHCPA4b0vNUnHtgvS/IA9I69VLunwbKxqalmxFRGkHlD52UPnwNg4TvmMoNRaFrV5pywM67A== MIME-Version: 1.0 X-Received: by 10.31.203.7 with SMTP id b7mr841173vkg.89.1461796819558; Wed, 27 Apr 2016 15:40:19 -0700 (PDT) Received: by 10.103.44.70 with HTTP; Wed, 27 Apr 2016 15:40:19 -0700 (PDT) In-Reply-To: References: Date: Wed, 27 Apr 2016 15:40:19 -0700 Message-ID: From: Aaron Wood To: Dave Taht Cc: Stephen Hemminger , cake@lists.bufferbloat.net, bloat Content-Type: multipart/alternative; boundary=001a114d893629e54f05317f186a Subject: Re: [Cake] [Bloat] are anyone playing with dpdk and vpp? X-BeenThere: cake@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Cake - FQ_codel the next generation List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Apr 2016 22:40:20 -0000 --001a114d893629e54f05317f186a Content-Type: text/plain; charset=UTF-8 > where the tx and rx rings are cleaned up in the same thread and there > is only one interrupt line for both. > > 51: 18 59244 253350 314273 PCI-MSI > 1572865-edge enp3s0-TxRx-0 > 52: 5 484274 141746 197260 PCI-MSI > 1572866-edge enp3s0-TxRx-1 > 53: 9 152225 29943 436749 PCI-MSI > 1572867-edge enp3s0-TxRx-2 > 54: 22 54327 299670 360356 PCI-MSI > 1572868-edge enp3s0-TxRx-3 > 56: 525343 513165 2355680 525593 PCI-MSI > 2097152-edge ath10k_pci > > and the ath10k only uses one interrupt. Maybe I'm wrong on my > assumptions, I'd think in today's multi-core environment that > processing tx and rx separately might be a win. (?) > The TX interrupt is used to free the SKB after the DMA from memory to the NIC, correct? (hard_start_xmit()?) -Aaron --001a114d893629e54f05317f186a Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable

=
where the tx and rx rings are cleaned up in the same thread and there
is only one interrupt line for both.

=C2=A0 51:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A018=C2=A0 =C2=A0 =C2=A0 59244=C2= =A0 =C2=A0 =C2=A0253350=C2=A0 =C2=A0 =C2=A0314273=C2=A0 =C2=A0PCI-MSI
1572865-edge=C2=A0 =C2=A0 =C2=A0 enp3s0-TxRx-0
=C2=A0 52:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 5=C2=A0 =C2=A0 =C2=A0484274=C2= =A0 =C2=A0 =C2=A0141746=C2=A0 =C2=A0 =C2=A0197260=C2=A0 =C2=A0PCI-MSI
1572866-edge=C2=A0 =C2=A0 =C2=A0 enp3s0-TxRx-1
=C2=A0 53:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 9=C2=A0 =C2=A0 =C2=A0152225=C2= =A0 =C2=A0 =C2=A0 29943=C2=A0 =C2=A0 =C2=A0436749=C2=A0 =C2=A0PCI-MSI
1572867-edge=C2=A0 =C2=A0 =C2=A0 enp3s0-TxRx-2
=C2=A0 54:=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A022=C2=A0 =C2=A0 =C2=A0 54327=C2= =A0 =C2=A0 =C2=A0299670=C2=A0 =C2=A0 =C2=A0360356=C2=A0 =C2=A0PCI-MSI
1572868-edge=C2=A0 =C2=A0 =C2=A0 enp3s0-TxRx-3
=C2=A0 56:=C2=A0 =C2=A0 =C2=A0525343=C2=A0 =C2=A0 =C2=A0513165=C2=A0 =C2=A0= 2355680=C2=A0 =C2=A0 =C2=A0525593=C2=A0 =C2=A0PCI-MSI
2097152-edge=C2=A0 =C2=A0 =C2=A0 ath10k_pci

and the ath10k only uses one interrupt. Maybe I'm wrong on my
assumptions, I'd think in today's multi-core environment that
processing tx and rx separately might be a win. (?)
The TX interrupt is used to free the SKB after the DMA from me= mory to the NIC, correct? (hard_start_xmit()?)

-Aa= ron
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