From: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
To: Cake List <cake@lists.bufferbloat.net>
Subject: [Cake] Latency target curiosity
Date: Thu, 7 May 2020 07:58:01 +0000 [thread overview]
Message-ID: <E8AAEA5E-98A9-48A7-86F3-BE4621B4074B@darbyshire-bryant.me.uk> (raw)
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Hi All,
As some of you are aware, I’ve been working on ’near live’ graphing of Cake’s stats under Openwrt, basically taking the output of ’tc -s -j qdisc foo’ and putting in relevant graphs.
A curiosity has arisen: I use diffserv4 mode on a 20Mbit egress link. Bulk tin has ‘capacity’ threshold of 1.2Mbit and because it’s a slow ’tin', the default target & interval values get overridden to 14.6ms and 109.6ms respectively. The 3 other tins are 5ms & 100ms defaults.
I have a backup job that bulk uploads 5 simultaneous flows to Onedrive. The sparse_delay, average_delay & peak_delay figures settle on 32, 38 & 43 ms respectively with around 9 drops per second on that tin.
I’m curious as to why the reported delays are over double the target latency?
Cheers,
Kevin D-B
gpg: 012C ACB2 28C6 C53E 9775 9123 B3A2 389B 9DE2 334A
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next reply other threads:[~2020-05-07 7:58 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-07 7:58 Kevin Darbyshire-Bryant [this message]
2020-05-07 8:09 ` Jonathan Morton
2020-05-07 9:11 ` Kevin Darbyshire-Bryant
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