From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp171.iad.emailsrvr.com (smtp171.iad.emailsrvr.com [207.97.245.171]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by huchra.bufferbloat.net (Postfix) with ESMTPS id 7EAC121F0B3 for ; Mon, 4 Feb 2013 08:41:30 -0800 (PST) Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp47.relay.iad1a.emailsrvr.com (SMTP Server) with ESMTP id 295423A81F7; Mon, 4 Feb 2013 11:41:29 -0500 (EST) X-Virus-Scanned: OK Received: from legacy16.wa-web.iad1a (legacy16.wa-web.iad1a.rsapps.net [192.168.4.106]) by smtp47.relay.iad1a.emailsrvr.com (SMTP Server) with ESMTP id 3CD4D3A846B; Mon, 4 Feb 2013 11:41:28 -0500 (EST) Received: from reed.com (localhost.localdomain [127.0.0.1]) by legacy16.wa-web.iad1a (Postfix) with ESMTP id D906D2450001; Mon, 4 Feb 2013 11:41:27 -0500 (EST) Received: by apps.rackspace.com (Authenticated sender: dpreed@reed.com, from: dpreed@reed.com) with HTTP; Mon, 4 Feb 2013 11:41:27 -0500 (EST) Date: Mon, 4 Feb 2013 11:41:27 -0500 (EST) From: dpreed@reed.com To: "Dave Taht" MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_20130204114127000000_99078" Importance: Normal X-Priority: 3 (Normal) X-Type: html In-Reply-To: References: <2450269.5e6MBhORZ9@markc> <1359915996.128612322@apps.rackspace.com> <1359940294.947925589@apps.rackspace.com> Message-ID: <1359996087.88714598@apps.rackspace.com> X-Mailer: webmail7.0 Cc: cerowrt-devel@lists.bufferbloat.net Subject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yurtlab X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Feb 2013 16:41:30 -0000 ------=_20130204114127000000_99078 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =0AI hadn't researched the HPC FMC requirement for 10 GigE one yet.=0A =0AT= he 1 GigE one is expensive, but not because of parts cost. This is the usu= al huge markup that goes with stuff sold to "Design Engineers" in companies= - because they can charge, they do.=0A =0AThe zedboard PMOD interface seem= s to be more marketing appropriate for "cheap" stuff. There is a PMOD for = 100baseT, so you could throw a few of those on your system very cheaply. = Since the interface to PMODs is 8-bit parallel, all you might need is the m= agnetics and PHY for GigE, and you could make a soft GigE controller in the= programmable logic part of the Zynq-7020. I'd have to check that the sign= alling rates would be sustainable across the PMOD connector.=0A =0ATo make = an FMC board, populate it with whatever GigE chip you like, etc. is trivial= . It should cost no more to fabricate than one of these little single chip= GigE PCIe cards you can buy. What chip would you like to use? I (or ot= hers) could design the board and BOM, kit it up for manufacturing (by, say,= Sunstone or other places that do PC boards and kitted assembly in small ru= ns).=0A =0ATrivial stuff - maybe one could even convince Digilent and/or Av= net to do the design/mfring.=0A =0AWouldn't it be a lot better to have a pl= uggable and completely flexible highly scalable monitoring unit that could = go down the wire level as needed, with the base cost being the $300 that a = Zedboard goes from?=0A =0AAnd it would be completely "open hardware" and :"= open source".=0A =0A-----Original Message-----=0AFrom: "Dave Taht" =0ASent: Sunday, February 3, 2013 8:47pm=0ATo: dpreed@reed.com= =0ACc: "Mark Constable" , cerowrt-devel@lists.bufferbloat.= net=0ASubject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yurtla= b=0A=0A=0A=0ADarn I wish I'd made it to that show today.=0A=0A=0AOn Sun, Fe= b 3, 2013 at 5:11 PM, <[mailto:dpreed@reed.com] dpreed@reed.com> wrote:=0A= =0A[http://www.prweb.com/releases/2012/2/prweb9154394.htm] http://www.prweb= .com/releases/2012/2/prweb9154394.htm (10 GigE FMC card)=0A =0A=0A impressi= ve. Seems to require a hpc (high pin count) board, which zed isn't.=0A=0A= =0A =0A[http://www.xilinx.com/products/boards-and-kits/1-2AJPAV.htm] http:/= /www.xilinx.com/products/boards-and-kits/1-2AJPAV.htm (1 GiGE FMC card)=0A= =0A625 eu. While I am painfully aware of how much it costs to step ahead of= the bleeding edge, I think the odds are pointing harder and harder at doin= g a non-fpga design that does what I want...=0A=0AI may go back to looking = at octeons or ti's new octeon killer.=0A=0AAnd/or leveraging a newer athero= s reference board.=0A =0A=0A =0A =0A-----Original Message-----=0AFrom: "Dav= e Taht" <[mailto:dave.taht@gmail.com] dave.taht@gmail.com>=0A=0ASent: Sunda= y, February 3, 2013 1:39pm=0ATo: [mailto:dpreed@reed.com] dpreed@reed.com= =0ACc: "Mark Constable" <[mailto:markc@renta.net] markc@renta.net>, [mailto= :cerowrt-devel@lists.bufferbloat.net] cerowrt-devel@lists.bufferbloat.net= =0A Subject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yurtlab= =0A=0A=0A=0A=0A=0A=0A=0AOn Sun, Feb 3, 2013 at 10:26 AM, <[mailto:dpreed@r= eed.com] dpreed@reed.com> wrote:=0A=0AIt would be trivial to do this with a= Zedboard.=0A=0AWell, need two network ports. Haven't figured out much on i= nterfacing the thing to offboard gear (I'd have liked it if it had a pci in= terface). So is interfacing up a second network card "trivial" on the I/Os = provided?=0A=0AAnd wanted esata, or some high speed disk I/O interface for = captures.=0A=0AI'd rather like to continue forward on the zedboard front. T= he prospect of designing an ethernet chip that actually could incorporate f= q_codel etc is very exciting. The RGII interface is available to access dir= ectly, in particular.=0A=0A=0A=0A=0A=0A=0A=0A =0A-----Original Message-----= =0AFrom: "Dave Taht" <[mailto:dave.taht@gmail.com] dave.taht@gmail.com>=0AS= ent: Sunday, February 3, 2013 1:17pm=0A To: "Mark Constable" <[mailto:markc= @renta.net] markc@renta.net>=0A Cc: [mailto:cerowrt-devel@lists.bufferbloat= .net] cerowrt-devel@lists.bufferbloat.net=0A Subject: Re: [Cerowrt-devel] s= tanford talk/deluged in hardware/yurtlab=0A=0A=0A=0AWell, I see it for 320.= Then you need to add a SSD, and a decent network card, and I suppose it co= uld be made to work. Awful big, tho, in an era where I can get 1/2TB on an = 2.5 inch SSD.=0A=0AWhat I'd wanted was closer to a dreamplug - 160 bucks, t= wo network ports, but with an internal SSD. bonus points if it fit into a 1= U rack and ate as little power as possible.=0A=0APrincipal use case here is= to be a "network monitor" with enough oomph to run stuff like cacti/mrtg/s= nmp tools, as well as do captures off of a mirrored switch port.=0A=0A=0A= =0A=0AOn Sun, Feb 3, 2013 at 10:10 AM, Dave Taht <[mailto:dave.taht@gmail.c= om] dave.taht@gmail.com> wrote:=0A=0A=0A=0A=0AOn Sun, Feb 3, 2013 at 10:03 = AM, Mark Constable <[mailto:markc@renta.net] markc@renta.net> wrote:=0A=0AO= n 2013-02-03 09:18am, Dave Taht wrote:=0A > I'm grumpy, as it doesn't have = an esata interface internally, apparently.=0A=0A[https://www.google.com?q= =3DHP+N40L+MicroServer] https://www.google.com?q=3DHP+N40L+MicroServer=0A= =0A I know this is no where near an embedded device but I just got one of t= hese=0A on sale (new model out) for $220 and I think it's the most useful a= ll-round=0A cheap server box I've ever seen. Some people have it running 16= GB ram and=0A I've got mine booting off an SSD via external eSATA. Very we= ll built with 2=0A x half height PCI slots (4 x eth port card?). Only missi= ng USB3 ports and=0A hot-swap drive space. And, very quiet with just an SSD= .=0A=0A=0AI'd be very interested to know how fast it could do packet header= captures.=0A=0ALine rate (gigE) would be good. =0A=0ADoes it do BQL? (what= is the onboard ethernet chips)=0A=0A=0A=0A=0A=0A=0A ______________________= _________________________=0A Cerowrt-devel mailing list=0A[mailto:Cerowrt-d= evel@lists.bufferbloat.net] Cerowrt-devel@lists.bufferbloat.net=0A[https://= lists.bufferbloat.net/listinfo/cerowrt-devel] https://lists.bufferbloat.net= /listinfo/cerowrt-devel=0A=0A=0A=0A=0A=0A-- =0ADave T=C3=A4ht=0A=0AFixing b= ufferbloat with cerowrt: [http://www.teklibre.com/cerowrt/subscribe.html] h= ttp://www.teklibre.com/cerowrt/subscribe.html=0A=0A=0A-- =0ADave T=C3=A4ht= =0A=0AFixing bufferbloat with cerowrt: [http://www.teklibre.com/cerowrt/sub= scribe.html] http://www.teklibre.com/cerowrt/subscribe.html=0A=0A=0A-- =0AD= ave T=C3=A4ht=0A=0AFixing bufferbloat with cerowrt: [http://www.teklibre.co= m/cerowrt/subscribe.html] http://www.teklibre.com/cerowrt/subscribe.html=0A= =0A=0A-- =0ADave T=C3=A4ht=0A=0AFixing bufferbloat with cerowrt: [http://ww= w.teklibre.com/cerowrt/subscribe.html] http://www.teklibre.com/cerowrt/subs= cribe.html ------=_20130204114127000000_99078 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

= I hadn't researched the HPC FMC requirement for 10 GigE one yet.

=0A

 

=0A

= The 1 GigE one is expensive, but not because of parts cost.  This is t= he usual huge markup that goes with stuff sold to "Design Engineers" in com= panies - because they can charge, they do.

=0A

 

=0A

The zedboard PMOD inte= rface seems to be more marketing appropriate for "cheap" stuff.  There= is a PMOD for 100baseT, so you could throw a few of those on your system v= ery cheaply.   Since the interface to PMODs is 8-bit parallel, al= l you might need is the magnetics and PHY for GigE, and you could make a so= ft GigE controller in the programmable logic part of the Zynq-7020.  I= 'd have to check that the signalling rates would be sustainable across the = PMOD connector.

=0A

 

=0A

To make an FMC board, populate it with whatever G= igE chip you like, etc. is trivial.  It should cost no more to fabrica= te than one of these little single chip GigE PCIe cards you can buy. &= nbsp; What chip would you like to use?   I (or others) could desi= gn the board and BOM, kit it up for manufacturing (by, say, Sunstone or oth= er places that do PC boards and kitted assembly in small runs).

=0A

 

=0A

T= rivial stuff - maybe one could even convince Digilent and/or Avnet to do th= e design/mfring.

=0A

 

=0A

Wouldn't it be a lot better to have a pluggable = and completely flexible highly scalable monitoring unit that could go down = the wire level as needed, with the base cost being the $300 that a Zedboard= goes from?

=0A

 

=0A

And it would be completely "open hardware" and :"open= source".

=0A

 

=0A

-----Original Message-----
From: "Dave Taht" <d= ave.taht@gmail.com>
Sent: Sunday, February 3, 2013 8:47pm
To: = dpreed@reed.com
Cc: "Mark Constable" <markc@renta.net>, cerowrt-= devel@lists.bufferbloat.net
Subject: Re: [Cerowrt-devel] stanford talk= /deluged in hardware/yurtlab

=0A
=0A

Darn I wish I'd made it to that sh= ow today.

=0A
On Sun, Feb 3, 2013 = at 5:11 PM, <dpreed@reed.com> wrote:
=0A
=0A

http://www.prweb= .com/releases/2012/2/prweb9154394.htm (10 GigE FMC card)

=0A

 

=0A=0A

impressive. Seems to require a hpc (high pin count) boa= rd, which zed isn't.

=0A
=0A

 

=0A

http://www.xilinx.com/products/boar= ds-and-kits/1-2AJPAV.htm (1 GiGE FMC card)

=0A
= =0A

625 eu. While I am painfully aware of how much it costs to st= ep ahead of the bleeding edge, I think the odds are pointing harder and har= der at doing a non-fpga design that does what I want...

I may go= back to looking at octeons or ti's new octeon killer.

And/or le= veraging a newer atheros reference board.

=0A
=0A<= p style=3D"margin:0;padding:0;margin: 0; padding: 0;"> 

=0A

 

=0A
-----Original Message-----
From: "Dave Taht" <dave.taht@gmail.com>
=0A=
=0A
Sent: Sunday, February 3, 2013 1:39pm
To: dpreed@reed.com
Cc: "Mark Constable" <markc@renta.net>, cerowrt-devel@lists.bufferbloat.net
Su= bject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yurtlab
<= br />
=0A
=0A
=0A
=0A


=0AOn Sun, Feb 3, 2013 at 10:26 AM, <dpreed@reed.com> wrote:
=0A
=0A

It would be trivial to do this with a Zedboard.

=0A<= /span>
=0A

Well, need two network ports. Haven't figu= red out much on interfacing the thing to offboard gear (I'd have liked it i= f it had a pci interface). So is interfacing up a second network card "triv= ial" on the I/Os provided?

And wanted esata, or some high speed = disk I/O interface for captures.

I'd rather like to continue for= ward on the zedboard front. The prospect of designing an ethernet chip that= actually could incorporate fq_codel etc is very exciting. The RGII interfa= ce is available to access directly, in particular.



<= br />
=0A
=0A
=0A
=0A

 

=0A

-----Original Message-----
From: "Dave Taht" <dave.taht@gmail.com&g= t;
Sent: Sunday, February 3, 2013 1:17pm
To: "Mark Constable" &l= t;markc@renta.net&= gt;
Cc: cerowrt-devel@lists.bufferbloat.net
Subject: Re: [Cer= owrt-devel] stanford talk/deluged in hardware/yurtlab

=0A=0A

Well, I see it = for 320. Then you need to add a SSD, and a decent network card, and I suppo= se it could be made to work. Awful big, tho, in an era where I can get 1/2T= B on an 2.5 inch SSD.

What I'd wanted was closer to a dreamplug = - 160 bucks, two network ports, but with an internal SSD. bonus points if i= t fit into a 1U rack and ate as little power as possible.

Princi= pal use case here is to be a "network monitor" with enough oomph to run stu= ff like cacti/mrtg/snmp tools, as well as do captures off of a mirrored swi= tch port.



=0A
On Sun, = Feb 3, 2013 at 10:10 AM, Dave Taht <dave.taht@gmail.com> w= rote:
=0A


=0A
=0A
On Sun, Feb 3, 2013 at 10:03 AM, Mark Constable <= span dir=3D"ltr"><m= arkc@renta.net> wrote:
=0A
=0A
On 2013-02-03 09:18am, Dave Taht wrote:
> I'm grump= y, as it doesn't have an esata interface internally, apparently.

=0Ahttps://www.google.com?q=3DHP+N40L+MicroServer

= I know this is no where near an embedded device but I just got one of these=
on sale (new model out) for $220 and I think it's the most useful al= l-round
cheap server box I've ever seen. Some people have it running = 16 GB ram and
I've got mine booting off an SSD via external eSATA. Ve= ry well built with 2
x half height PCI slots (4 x eth port card?). On= ly missing USB3 ports and
hot-swap drive space. And, very quiet with = just an SSD.
=0A
=0A

I'd be very intereste= d to know how fast it could do packet header captures.

Line rate= (gigE) would be good.

Does it do BQL? (what is the onboard eth= ernet chips)




=0A
=0A

_______________________________________________=
Cerowrt-devel mailing list
Cerowrt-devel@lists.bufferbloat.net
https://lists.bufferbloat.net/listinfo/cerowrt-devel
=0A
=0A
=0A

=0A
=0A

-- Dave T=C3=A4ht

Fixing bufferbloat with cerowrt: http://www= .teklibre.com/cerowrt/subscribe.html
=0A
=0A
=0A<= /div>=0A


--
Dave T=C3=A4ht

Fixing bufferb= loat with cerowrt: http://www.teklibre.com/cerowrt/subscribe.html=0A
=0A
=0A
=0A
=0A


--=
Dave T=C3=A4ht

Fixing bufferbloat with cerowrt: http:= //www.teklibre.com/cerowrt/subscribe.html
=0A
=0A
=0A=0A
=0A


--
Dave T=C3=A4ht

Fixing bufferbloat with cerowrt: http://www.teklibre.com/cerowrt/s= ubscribe.html ------=_20130204114127000000_99078--