From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp111.iad.emailsrvr.com (smtp111.iad.emailsrvr.com [207.97.245.111]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by huchra.bufferbloat.net (Postfix) with ESMTPS id 2B21821F107 for ; Mon, 4 Feb 2013 19:41:26 -0800 (PST) Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp41.relay.iad1a.emailsrvr.com (SMTP Server) with ESMTP id 53CDE29085B; Mon, 4 Feb 2013 22:41:24 -0500 (EST) X-Virus-Scanned: OK Received: from legacy7.wa-web.iad1a (legacy7.wa-web.iad1a.rsapps.net [192.168.2.216]) by smtp41.relay.iad1a.emailsrvr.com (SMTP Server) with ESMTP id 1B28A2904E1; Mon, 4 Feb 2013 22:41:24 -0500 (EST) Received: from reed.com (localhost [127.0.0.1]) by legacy7.wa-web.iad1a (Postfix) with ESMTP id 0C1223200B0; Mon, 4 Feb 2013 22:41:24 -0500 (EST) Received: by apps.rackspace.com (Authenticated sender: dpreed@reed.com, from: dpreed@reed.com) with HTTP; Mon, 4 Feb 2013 22:41:24 -0500 (EST) Date: Mon, 4 Feb 2013 22:41:24 -0500 (EST) From: dpreed@reed.com To: "Dave Taht" MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_20130204224124000000_11341" Importance: Normal X-Priority: 3 (Normal) X-Type: html In-Reply-To: References: Message-ID: <1360035684.047916708@apps.rackspace.com> X-Mailer: webmail7.0 Cc: cerowrt-devel@lists.bufferbloat.net Subject: Re: [Cerowrt-devel] packet capture hardware X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Feb 2013 03:41:26 -0000 ------=_20130204224124000000_11341 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =0AYou can buy add-on 10/100 Pmods for $30 that would work on the zedboard = from Digilent. No need to design one.=0A =0AAlso, I just dug into the Zynq= -7000 Tech Ref Manuals, and the Zedboard documentation. The Zynq7020 on t= he Zedboard has two 10/100/1000 (GigE) controllers. The board only has one= external PHY (Broadcom). But the "pins" of the other GigE controller are = connected to the PL (Programmable Logic) and can be routed as RGMII or GMII= signals (even tapped by PL along the way) to SelectI/O pins on Pmod or FMC= interfaces. So if you want just one more 1 GigE port, you just have to m= ake a tiny board that holds one PHY chip of your choice. I can probably arr= ange to have a couple hundred made in Ireland for almost nothing per board.= One of my buddies here in Boston does a lot of small hardware boards for= medical electronics, and is partnered with a PCB maker that is very inexpe= nsive for small runs of simple boards.=0A =0AFor prototyping for a small gr= oup, one could make a "single board" a few inches across and slice it into = maybe 10 boards with a single FMC connector, a GigE PHY and RJ45 as the onl= y pieces. The FMC would be on one side, and the other side would be the PH= Y and RJ45. the "single board" would be maybe $125 bucks plus kit, quantit= y one. That would give you 10 adapters for under $20 each, all in.=0A =0AN= ow the idea of going from FPGA to ASIC is not really that interesting - I'm= much more interested in hobbyist or prosumer network debugging stuff. Ye= ah, the quantity one cost of the Zynq7020 is high (as are most FPGAs). I'v= e never talked to Avnet or Digilent about whether they'd be interested in t= his sort of thing. At the Media Lab and CSAIL, all the gear needed to ass= emble short runs with tape-and-reel parts and reflow soldering are pretty a= vailable if its for a good cause.=0A =0AI also probably could interest Vanu= Bose (his company does design/manufacturing in India for his SDR products)= in maybe helping, if the project involves perhaps extensibility to debuggi= ng various cellular networking deployments, etc. He is selling a lot of ce= llular data gear for the Indian rural market, at very low costs compared to= the high cost of non-SDR stuff.=0A =0A =0A-----Original Message-----=0AFro= m: "Dave Taht" =0ASent: Monday, February 4, 2013 12:48= pm=0ATo: dpreed@reed.com=0ACc: "Mark Constable" , cerowrt-= devel@lists.bufferbloat.net=0ASubject: packet capture hardware=0A=0A=0A=0AC= hanging the subject line to reflect this line of discourse.=0A=0A=0AOn Mon,= Feb 4, 2013 at 8:41 AM, <[mailto:dpreed@reed.com] dpreed@reed.com> wrote:= =0A=0AI hadn't researched the HPC FMC requirement for 10 GigE one yet.=0A = =0AThe 1 GigE one is expensive, but not because of parts cost. This is the= usual huge markup that goes with stuff sold to "Design Engineers" in compa= nies - because they can charge, they do.=0A=0AWell, it is also a function o= f volume. as a counter example, we can probably leverage an upcoming manufa= cturing run of one of atheros's newer chipsets, designed close to a cerowrt= -able, debloatable spec, for about 30 bucks in 10k qtys. This still sort of= implies a change in cerowrt's focus from "fixing hardware you can get off = the shelf" to *making something* arduino-raspberri pi like, but has a great= deal of appeal for me. (inspiration: meraki) I am sufficiently annoyed at = the entire industry at this point. I am insufficiently wealthy. =0A=0AAnywa= y, that chipset probably isn't fast enough to do packet captures at line ra= te, so to continue on the thread of "designing a good box for packet captur= es" but sort of half retaining the cerowrt concept and wandering around oth= ers, in this email....=0A=0AI think there is a real market need for somethi= ng in the SFP form factor that can do high rate packet captures and other s= orts of analysis. I imagine a SFP in, and Esata out going into a router wou= ld be a useful diagnostic tool (and also something the NSA would love, whic= h I have ambiguous feelings about)=0A=0AIt could also be priced appropriate= ly and maybe make some money.=0A =0AI think there is also a market need for= something that can be an analysis box/home router that can also do capture= s at typical rates in the home (20-30Mbit), but that's still just above wha= t a wndr3800 can do when last I tried. (it's mostly bound by the usb interf= ace actually)=0A=0AThe dreamplug hw can do that, as best as I recall (getti= ng one shortly)=0A=0A=0A =0AThe zedboard PMOD interface seems to be more ma= rketing appropriate for "cheap" stuff. There is a PMOD for 100baseT, so yo= u could throw a few of those on your system very cheaply. Since the inter= face to PMODs is 8-bit parallel, all you might need is the magnetics and PH= Y for GigE, and you could make a soft GigE controller in the programmable l= ogic part of the Zynq-7020.=0A=0AI'd certainly like to make an eth controll= er capable of handling TSO/UFO and breaking them up with fq/codel at the lo= west possible level. On the other hand I'm pretty sure a dual core a9 box i= s fast enough to drive gigE with minimal buffering (but haven't played with= the zedboard enough to know. I do know the driver isn't bql'd. It's on my = todo list)=0A=0AOne of the things I'm vague about is the path to making sil= icon, starting with a FPGA design like this. Say we solve the universe:=0A= =0A* Build a better wifi interface (and other forms of wireless interface)= =0A * Do gigE switching/routing/rate limiting with fq/codel in hw=0A* Has a= dsl and/or cable modem functionality=0A* Earthquake detector (just throwing= that in there! :) )=0A=0AWhat's the path to cost reducing that to, say, 15= bucks a chip in 3 years?=0AI'd have to check that the signalling rates wou= ld be sustainable across the PMOD connector.=0A=0A100Mbit is enough for the= "home gateway" scenario.=0A =0A=0A =0ATo make an FMC board, populate it wi= th whatever GigE chip you like, etc. is trivial. It should cost no more to= fabricate than one of these little single chip GigE PCIe cards you can buy= . What chip would you like to use? I (or others) could design the board= and BOM, kit it up for manufacturing (by, say, Sunstone or other places th= at do PC boards and kitted assembly in small runs).=0A=0AI like the idea of= a soft chip on the fpga myself, actually. I'd like to get smarter logic in= side the tx ring. I don't care for any of the current generation of etherne= t chips very much. The ar71xx in cero has the advantage of being rather sim= ple, the e1000e is a very common chip, too. The realtek is terrible with to= ns of errata.=0A=0ASo to just use a phy... well, broadcom's common phys nee= d a nda to look at, so do marvel's. It would be interesting to pursue makin= g a switch/router actually out of a sufficient number of phys, if there is = sufficient I/Os available on the fpga. Something like the vyatta...=0A=0Aan= d with a soft eth design it could scale up to 10GigE or higher.=0A=0A=0A = =0ATrivial stuff - maybe one could even convince Digilent and/or Avnet to d= o the design/mfring.=0A=0AI would like to think that the latency advantage = of making a debloated box would convince some people, like wall street, and= large scale buyers to get involved. That said, I look at the hits on thing= s like the water videos at modena and the uphill battle with multiple manuf= acturers thus far and get discouraged... =0A =0A=0A =0AWouldn't it be a lot= better to have a pluggable and completely flexible highly scalable monitor= ing unit that could go down the wire level as needed, with the base cost be= ing the $300 that a Zedboard goes from?=0A=0AIt looks like the fpga chip it= self is 220 presently. I am not sure how rapidly that will drop with time o= r volume.=0A=0Aooh, I see they have a milspec version (my hobby is space st= uff)=0A =0A=0A =0AAnd it would be completely "open hardware" and :"open sou= rce".=0A=0AI would so totally dig that. The number of VCs in my rolodex is = rather small. =0A=0AI agree with you that the zedboard is "the raspberri pi= of high speed digital logic" and that a zillion things can/will be done wi= th it. However it's at a painful price point presently for most "normal" pe= ople. This is an advantage, actually, given some of the target markets...= =0A=0A(I kind of hate it when I wear my business hat rather than my enginee= ring one)=0A=0AI think the scope of designing a full fledged standalone zed= board-like board, =0Aone that fits into the home router role, or a packet c= apture role, or a SFP slot,=0A is rather large, and would need a payoff at = the end...=0A=0AEven something on the scale of the netfpga project over at = stanford (which only saw about 2000 manufactured and huge uni support), wil= l take time and money. It would be very fun, and potentially profitable at = the end, but as a hobby project... the learning curve is steep, the skills = required very diverse. (yes, fun, yes needs a community to form around it)= =0A=0A(And cero as it stands eats way too much of my time and I really woul= d like to get someone else(s) building it so I can focus on more nagging is= sues up the stack)=0A=0AAs for designing an add-on 100Mbit board to the zed= board, much easier. I'm not huge on the PMOD connectors (fragile. Worse, th= e SD card sticks out the side, and I already broke one zedboard's SD connec= tor off), and a big unknown is how fast they can be driven....=0A=0A=0A=0A = =0A =0A-----Original Message-----=0AFrom: "Dave Taht" <[mailto:dave.taht@gm= ail.com] dave.taht@gmail.com>=0A=0ASent: Sunday, February 3, 2013 8:47pm=0A= To: [mailto:dpreed@reed.com] dpreed@reed.com=0ACc: "Mark Constable" <[mailt= o:markc@renta.net] markc@renta.net>, [mailto:cerowrt-devel@lists.bufferbloa= t.net] cerowrt-devel@lists.bufferbloat.net=0A Subject: Re: [Cerowrt-devel] = stanford talk/deluged in hardware/yurtlab=0A=0A=0A=0A=0A=0ADarn I wish I'd = made it to that show today.=0A=0A=0AOn Sun, Feb 3, 2013 at 5:11 PM, <[mail= to:dpreed@reed.com] dpreed@reed.com> wrote:=0A=0A[http://www.prweb.com/rele= ases/2012/2/prweb9154394.htm] http://www.prweb.com/releases/2012/2/prweb915= 4394.htm (10 GigE FMC card)=0A =0A=0A impressive. Seems to require a hpc (h= igh pin count) board, which zed isn't.=0A=0A=0A =0A[http://www.xilinx.com/p= roducts/boards-and-kits/1-2AJPAV.htm] http://www.xilinx.com/products/boards= -and-kits/1-2AJPAV.htm (1 GiGE FMC card)=0A=0A625 eu. While I am painfully = aware of how much it costs to step ahead of the bleeding edge, I think the = odds are pointing harder and harder at doing a non-fpga design that does wh= at I want...=0A=0AI may go back to looking at octeons or ti's new octeon ki= ller.=0A=0AAnd/or leveraging a newer atheros reference board.=0A=0A=0A =0A = =0A-----Original Message-----=0AFrom: "Dave Taht" <[mailto:dave.taht@gmail.= com] dave.taht@gmail.com>=0A=0ASent: Sunday, February 3, 2013 1:39pm=0ATo: = [mailto:dpreed@reed.com] dpreed@reed.com=0ACc: "Mark Constable" <[mailto:ma= rkc@renta.net] markc@renta.net>, [mailto:cerowrt-devel@lists.bufferbloat.ne= t] cerowrt-devel@lists.bufferbloat.net=0A Subject: Re: [Cerowrt-devel] stan= ford talk/deluged in hardware/yurtlab=0A=0A=0A=0A=0A=0A=0A=0AOn Sun, Feb 3,= 2013 at 10:26 AM, <[mailto:dpreed@reed.com] dpreed@reed.com> wrote:=0A=0A= It would be trivial to do this with a Zedboard.=0A=0AWell, need two network= ports. Haven't figured out much on interfacing the thing to offboard gear = (I'd have liked it if it had a pci interface). So is interfacing up a secon= d network card "trivial" on the I/Os provided?=0A=0AAnd wanted esata, or so= me high speed disk I/O interface for captures.=0A=0AI'd rather like to cont= inue forward on the zedboard front. The prospect of designing an ethernet c= hip that actually could incorporate fq_codel etc is very exciting. The RGII= interface is available to access directly, in particular.=0A=0A=0A=0A=0A= =0A=0A=0A =0A-----Original Message-----=0AFrom: "Dave Taht" <[mailto:dave.t= aht@gmail.com] dave.taht@gmail.com>=0ASent: Sunday, February 3, 2013 1:17pm= =0A To: "Mark Constable" <[mailto:markc@renta.net] markc@renta.net>=0A Cc: = [mailto:cerowrt-devel@lists.bufferbloat.net] cerowrt-devel@lists.bufferbloa= t.net=0A Subject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yur= tlab=0A=0A=0A=0AWell, I see it for 320. Then you need to add a SSD, and a d= ecent network card, and I suppose it could be made to work. Awful big, tho,= in an era where I can get 1/2TB on an 2.5 inch SSD.=0A=0AWhat I'd wanted w= as closer to a dreamplug - 160 bucks, two network ports, but with an intern= al SSD. bonus points if it fit into a 1U rack and ate as little power as po= ssible.=0A=0APrincipal use case here is to be a "network monitor" with enou= gh oomph to run stuff like cacti/mrtg/snmp tools, as well as do captures of= f of a mirrored switch port.=0A=0A=0A=0A=0AOn Sun, Feb 3, 2013 at 10:10 AM,= Dave Taht <[mailto:dave.taht@gmail.com] dave.taht@gmail.com> wrote:=0A=0A= =0A=0A=0AOn Sun, Feb 3, 2013 at 10:03 AM, Mark Constable <[mailto:markc@ren= ta.net] markc@renta.net> wrote:=0A=0AOn 2013-02-03 09:18am, Dave Taht wrote= :=0A > I'm grumpy, as it doesn't have an esata interface internally, appare= ntly.=0A=0A[https://www.google.com?q=3DHP+N40L+MicroServer] https://www.goo= gle.com?q=3DHP+N40L+MicroServer=0A=0A I know this is no where near an embed= ded device but I just got one of these=0A on sale (new model out) for $220 = and I think it's the most useful all-round=0A cheap server box I've ever se= en. Some people have it running 16 GB ram and=0A I've got mine booting off = an SSD via external eSATA. Very well built with 2=0A x half height PCI slot= s (4 x eth port card?). Only missing USB3 ports and=0A hot-swap drive space= . And, very quiet with just an SSD.=0A=0A=0AI'd be very interested to know = how fast it could do packet header captures.=0A=0ALine rate (gigE) would be= good. =0A=0ADoes it do BQL? (what is the onboard ethernet chips)=0A=0A=0A= =0A=0A=0A=0A _______________________________________________=0A Cerowrt-dev= el mailing list=0A[mailto:Cerowrt-devel@lists.bufferbloat.net] Cerowrt-deve= l@lists.bufferbloat.net=0A[https://lists.bufferbloat.net/listinfo/cerowrt-d= evel] https://lists.bufferbloat.net/listinfo/cerowrt-devel=0A=0A=0A=0A=0A= =0A-- =0ADave T=C3=A4ht=0A=0AFixing bufferbloat with cerowrt: [http://www.t= eklibre.com/cerowrt/subscribe.html] http://www.teklibre.com/cerowrt/subscri= be.html=0A=0A=0A-- =0ADave T=C3=A4ht=0A=0AFixing bufferbloat with cerowrt: = [http://www.teklibre.com/cerowrt/subscribe.html] http://www.teklibre.com/ce= rowrt/subscribe.html=0A=0A=0A-- =0ADave T=C3=A4ht=0A=0AFixing bufferbloat w= ith cerowrt: [http://www.teklibre.com/cerowrt/subscribe.html] http://www.te= klibre.com/cerowrt/subscribe.html=0A=0A=0A-- =0ADave T=C3=A4ht=0A=0AFixing = bufferbloat with cerowrt: [http://www.teklibre.com/cerowrt/subscribe.html] = http://www.teklibre.com/cerowrt/subscribe.html=0A=0A=0A-- =0ADave T=C3=A4ht= =0A=0AFixing bufferbloat with cerowrt: [http://www.teklibre.com/cerowrt/sub= scribe.html] http://www.teklibre.com/cerowrt/subscribe.html ------=_20130204224124000000_11341 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

= You can buy add-on 10/100 Pmods for $30 that would work on the zedboard fro= m Digilent.  No need to design one.

=0A

 

=0A

Also, I just dug into th= e Zynq-7000 Tech Ref Manuals, and the Zedboard documentation.   T= he Zynq7020 on the Zedboard has two 10/100/1000 (GigE) controllers.  T= he board only has one external PHY (Broadcom).  But the "pins" of the = other GigE controller are connected to the PL (Programmable Logic) and can = be routed as RGMII or GMII signals (even tapped by PL along the way) to Sel= ectI/O pins on Pmod or FMC interfaces.   So if you want just one = more 1 GigE port, you just have to make a tiny board that holds one PHY chi= p of your choice. I can probably arrange to have a couple hundred made in I= reland for almost nothing per board.   One of my buddies here in = Boston does a lot of small hardware boards for medical electronics, and is = partnered with a PCB maker that is very inexpensive for small runs of simpl= e boards.

=0A

 

=0A

For prototyping for a small group, one could make a "si= ngle board" a few inches across and slice it into maybe 10 boards with a si= ngle FMC connector, a GigE PHY and RJ45 as the only pieces.  The FMC w= ould be on one side, and the other side would be the PHY and RJ45.  th= e "single board" would be maybe $125 bucks plus kit, quantity one.  Th= at would give you 10 adapters for under $20 each, all in.

=0A

 

=0A

Now the= idea of going from FPGA to ASIC is not really that interesting - I'm much = more interested in hobbyist or prosumer network debugging stuff.  = ; Yeah, the quantity one cost of the Zynq7020 is high (as are most FPGAs).&= nbsp; I've never talked to Avnet or Digilent about whether they'd be intere= sted in this sort of thing.   At the Media Lab and CSAIL, all the= gear needed to assemble short runs with tape-and-reel parts and reflow sol= dering are pretty available if its for a good cause.

=0A

 

=0A

I also proba= bly could interest Vanu Bose (his company does design/manufacturing in Indi= a for his SDR products) in maybe helping, if the project involves perhaps e= xtensibility to debugging various cellular networking deployments, etc.&nbs= p; He is selling a lot of cellular data gear for the Indian rural market, a= t very low costs compared to the high cost of non-SDR stuff.

=0A

 

=0A

&nbs= p;

=0A

-----Original Message-----
F= rom: "Dave Taht" <dave.taht@gmail.com>
Sent: Monday, February 4,= 2013 12:48pm
To: dpreed@reed.com
Cc: "Mark Constable" <markc@= renta.net>, cerowrt-devel@lists.bufferbloat.net
Subject: packet cap= ture hardware

=0A
=0A

Changing the subject line to reflect this line of= discourse.

=0A
On Mon, Feb 4, 201= 3 at 8:41 AM, <dpreed@reed.com> wrote:
=0A
=0A

I hadn't researched the= HPC FMC requirement for 10 GigE one yet.

=0A

 

=0A

The 1 GigE one is expensive, but not because of parts = cost.  This is the usual huge markup that goes with stuff sold to "Des= ign Engineers" in companies - because they can charge, they do.

=0A
=0A

Well, it is also a function of volume. as a co= unter example, we can probably leverage an upcoming manufacturing run of on= e of atheros's newer chipsets, designed close to a cerowrt-able, debloatabl= e spec, for about 30 bucks in 10k qtys. This still sort of implies a change= in cerowrt's focus from "fixing hardware you can get off the shelf" to *ma= king something* arduino-raspberri pi like, but has a great deal of appeal f= or me. (inspiration: meraki) I am sufficiently annoyed at the entire indust= ry at this point. I am insufficiently wealthy.

Anyway, that chi= pset probably isn't fast enough to do packet captures at line rate, so to c= ontinue on the thread of "designing a good box for packet captures" but sor= t of half retaining the cerowrt concept and wandering around others, in thi= s email....

I think there is a real market need for something in= the SFP form factor that can do high rate packet captures and other sorts = of analysis. I imagine a SFP in, and Esata out going into a router would be= a useful diagnostic tool (and also something the NSA would love, which I h= ave ambiguous feelings about)

It could also be priced appropriat= ely and maybe make some money.

I think there is also a market n= eed for something that can be an analysis box/home router that can also do = captures at typical rates in the home (20-30Mbit), but that's still just ab= ove what a wndr3800 can do when last I tried. (it's mostly bound by the usb= interface actually)

The dreamplug hw can do that, as best as I = recall (getting one shortly)

=0A
=0A

 

=0A

The zedboard PMOD interface seems to be mo= re marketing appropriate for "cheap" stuff.  There is a PMOD for 100ba= seT, so you could throw a few of those on your system very cheaply. &n= bsp; Since the interface to PMODs is 8-bit parallel, all you might need is = the magnetics and PHY for GigE, and you could make a soft GigE controller i= n the programmable logic part of the Zynq-7020.

=0A
= =0A

I'd certainly like to make an eth controller capable of handl= ing TSO/UFO and breaking them up with fq/codel at the lowest possible level= . On the other hand I'm pretty sure a dual core a9 box is fast enough to dr= ive gigE with minimal buffering (but haven't played with the zedboard enoug= h to know. I do know the driver isn't bql'd. It's on my todo list)
One of the things I'm vague about is the path to making silicon, startin= g with a FPGA design like this. Say we solve the universe:

* Bui= ld a better wifi interface (and other forms of wireless interface)
* = Do gigE switching/routing/rate limiting with fq/codel in hw
* Has adsl= and/or cable modem functionality
* Earthquake detector (just throwing= that in there! :) )

What's the path to cost reducing that to, s= ay, 15 bucks a chip in 3 years?
=0A
=0A

I'd have to check that the signalling rates = would be sustainable across the PMOD connector.

=0A
= =0A

100Mbit is enough for the "home gateway" scenario.

=0A
=0A

To ma= ke an FMC board, populate it with whatever GigE chip you like, etc. is triv= ial.  It should cost no more to fabricate than one of these little sin= gle chip GigE PCIe cards you can buy.   What chip would you like = to use?   I (or others) could design the board and BOM, kit it up= for manufacturing (by, say, Sunstone or other places that do PC boards and= kitted assembly in small runs).

=0A
=0A

I = like the idea of a soft chip on the fpga myself, actually. I'd like to get = smarter logic inside the tx ring. I don't care for any of the current gener= ation of ethernet chips very much. The ar71xx in cero has the advantage of = being rather simple, the e1000e is a very common chip, too. The realtek is = terrible with tons of errata.

So to just use a phy... well, broa= dcom's common phys need a nda to look at, so do marvel's. It would be inter= esting to pursue making a switch/router actually out of a sufficient number= of phys, if there is sufficient I/Os available on the fpga. Something like= the vyatta...

and with a soft eth design it could scale up to 1= 0GigE or higher.

=0A
<= span style=3D"font-family: times new roman;">=0A

 

=0A

Trivial stuff - maybe one could even convince Digilent= and/or Avnet to do the design/mfring.

=0A
=0A
I would like to think that the latency advantage of making a debloated = box would convince some people, like wall street, and large scale buyers to= get involved. That said, I look at the hits on things like the water video= s at modena and the uphill battle with multiple manufacturers thus far and = get discouraged...

=0A
=0A

 

=0A

Wouldn't it be a lot better to have a pluggable an= d completely flexible highly scalable monitoring unit that could go down th= e wire level as needed, with the base cost being the $300 that a Zedboard g= oes from?

=0A
=0A

It looks like the fpga ch= ip itself is 220 presently. I am not sure how rapidly that will drop with t= ime or volume.

ooh, I see they have a milspec version (my hobby = is space stuff)

=0A
<= span style=3D"font-family: times new roman;">=0A

 

=0A

And it would be completely "open hardware" and :"open = source".

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I would so totally dig tha= t. The number of VCs in my rolodex is rather small.

I agree wit= h you that the zedboard is "the raspberri pi of high speed digital logic" a= nd that a zillion things can/will be done with it. However it's at a painfu= l price point presently for most "normal" people. This is an advantage, act= ually, given some of the target markets...

(I kind of hate it wh= en I wear my business hat rather than my engineering one)

I thin= k the scope of designing a full fledged standalone zedboard-like board, one that fits into the home router role, or a packet capture role, or a = SFP slot,
is rather large, and would need a payoff at the end...

Even something on the scale of the netfpga project over at stanford = (which only saw about 2000 manufactured and huge uni support), will take ti= me and money. It would be very fun, and potentially profitable at the end, = but as a hobby project... the learning curve is steep, the skills required = very diverse. (yes, fun, yes needs a community to form around it)

(And cero as it stands eats way too much of my time and I really would li= ke to get someone else(s) building it so I can focus on more nagging issues= up the stack)

As for designing an add-on 100Mbit board to the z= edboard, much easier. I'm not huge on the PMOD connectors (fragile. Worse, = the SD card sticks out the side, and I already broke one zedboard's SD conn= ector off), and a big unknown is how fast they can be driven....


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-----Original Message-----
From: "Dave = Taht" <dave.tah= t@gmail.com>
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Sent: Sunday, Februar= y 3, 2013 8:47pm
To: dpreed@reed.com
Cc: "Mark Constable" <markc@renta.net>, cerowrt-devel@lists.= bufferbloat.net
Subject: Re: [Cerowrt-devel] stanford talk/deluge= d in hardware/yurtlab

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Darn I = wish I'd made it to that show today.

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On Sun, Feb 3, 2013 at 5:11 PM, <dpreed@reed.com> wrot= e:
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http://www.prweb.com/releases/2012/2/prweb9154394.htm (10 G= igE FMC card)

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impressive. Seems to requir= e a hpc (high pin count) board, which zed isn't.

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=0Ahttp://= www.xilinx.com/products/boards-and-kits/1-2AJPAV.htm (1 GiGE FMC card)<= /p>=0A
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625 eu. While I am painfully aware = of how much it costs to step ahead of the bleeding edge, I think the odds a= re pointing harder and harder at doing a non-fpga design that does what I w= ant...

I may go back to looking at octeons or ti's new octeon ki= ller.

And/or leveraging a newer atheros reference board.
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&nb= sp;

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-----Original Message-----
From: "Dave Taht" <dave.taht@gmail.com&= gt;
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Sent: Sunday, February 3, 2013 1:39pm
To: dpreed@reed.com
= Cc: "Mark Constable" <markc@renta.net>, cerowrt-devel@lists.bufferbloat.net
Sub= ject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yurtlab
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On Sun, Feb 3, 2013 at 10:26 AM, <dpreed@reed.com> wrote:
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It would be trivial to do this with a Zedboard.

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Well, need two network ports. Haven't figured out much= on interfacing the thing to offboard gear (I'd have liked it if it had a p= ci interface). So is interfacing up a second network card "trivial" on the = I/Os provided?

And wanted esata, or some high speed disk I/O int= erface for captures.

I'd rather like to continue forward on the = zedboard front. The prospect of designing an ethernet chip that actually co= uld incorporate fq_codel etc is very exciting. The RGII interface is availa= ble to access directly, in particular.




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-----Original Message-----
From: "Dave Taht" <dave.taht@gmail.com>
Sen= t: Sunday, February 3, 2013 1:17pm
To: "Mark Constable" <markc@renta.net>
= Cc: cerowrt-devel@lists.bufferbloat.net
Subject: Re: [Cerowrt-deve= l] stanford talk/deluged in hardware/yurtlab

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Well, I see it for 320. = Then you need to add a SSD, and a decent network card, and I suppose it cou= ld be made to work. Awful big, tho, in an era where I can get 1/2TB on an 2= .5 inch SSD.

What I'd wanted was closer to a dreamplug - 160 buc= ks, two network ports, but with an internal SSD. bonus points if it fit int= o a 1U rack and ate as little power as possible.

Principal use c= ase here is to be a "network monitor" with enough oomph to run stuff like c= acti/mrtg/snmp tools, as well as do captures off of a mirrored switch port.=



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On Sun, Feb 3, 20= 13 at 10:10 AM, Dave Taht <dave.taht@gmail.com> wrote:
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On Sun, Feb 3, 2013 at 10:03 AM, Mark Constable <markc@ren= ta.net> wrote:
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On 2013-02-03 09:18am, Dave Taht wrote:
> I'm grumpy, as i= t doesn't have an esata interface internally, apparently.

= =0Ahttps://www.google.com?q=3DHP+N40L+MicroServer

I know = this is no where near an embedded device but I just got one of these
= on sale (new model out) for $220 and I think it's the most useful all-round=
cheap server box I've ever seen. Some people have it running 16 GB r= am and
I've got mine booting off an SSD via external eSATA. Very well= built with 2
x half height PCI slots (4 x eth port card?). Only miss= ing USB3 ports and
hot-swap drive space. And, very quiet with just an= SSD.
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I'd be very interested to kn= ow how fast it could do packet header captures.

Line rate (gigE)= would be good.

Does it do BQL? (what is the onboard ethernet c= hips)




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_______________________________________________
= Cerowrt-devel mailing list
Cerowrt-devel@lists.bufferbloat.net
= https://lists.bufferbloat.net/listinfo/cerowrt-devel
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--
Dav= e T=C3=A4ht

Fixing bufferbloat with cerowrt: http://www.teklib= re.com/cerowrt/subscribe.html
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--
Dave T=C3=A4ht

Fixing bufferbloat = with cerowrt: http://www.teklibre.com/cerowrt/subscribe.html
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--
Dave T=C3=A4ht

Fixing bufferbloat with cerowrt: http://www.t= eklibre.com/cerowrt/subscribe.html
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--
Dave T=C3=A4ht

= Fixing bufferbloat with cerowrt: http://www.teklibre.com/cerowrt/subscrib= e.html
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=

--
Dave T=C3=A4ht

Fixing bufferbloat with cero= wrt: http://www.teklibre.com/cerowrt/subscribe.html ------=_20130204224124000000_11341--