Development issues regarding the cerowrt test router project
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* Re: [Cerowrt-devel] expressobin
@ 2018-08-01 12:49 dpreed
  2018-08-01 12:56 ` Outback Dingo
  2018-08-01 20:06 ` Dave Taht
  0 siblings, 2 replies; 10+ messages in thread
From: dpreed @ 2018-08-01 12:49 UTC (permalink / raw)
  To: Toke Høiland-Jørgensen
  Cc: Dave Taht, Daniel Ezell, Cake List, cerowrt-devel

Yeah. Small FF 2 port Celeron board is what I use. And I have a 4 port Atom that runs like a bat out of hell. 

Currenty fiddling with Xilinx Dev boards, just put packet processing in FPGA for Cake, and no problem with 2.5 - 10 Gb/sec. Just need a free piece of low level SFP+ interfacing logic.

My use case is using the open ChipLink/TileLink bus from RISCV rather than PCIe, making something that might be an open source ASIC design.


-----Original Message-----
From: "Toke Høiland-Jørgensen" <toke@toke.dk>
Sent: Wed, Aug 1, 2018 at 5:23 am
To: "Dave Taht" <dave.taht@gmail.com>, "Daniel Ezell" <dezell@stonescry.com>
Cc: "Dave Taht" <dave.taht@gmail.com>, "Daniel Ezell" <dezell@stonescry.com>, "Cake List" <cake@lists.bufferbloat.net>, cerowrt-devel@lists.bufferbloat.net
Subject: Re: [Cerowrt-devel] expressobin

Dave Taht  writes:

> It turns out it's just two ethernets with one, connected to a 2 port
> switch. Not what I wanted. I'd wanted something different from the
> apu2 or edgerouter X to play with, and I know the mvneta driver was
> bql'd.

I bought one of these to play with:
https://teklager.se/en/products/routers/tlsense-i3-4lan

x86 (i3 processor), four real ethernet ports, and passively cooled. A
bit pricy, though; more than $400... But doubles well as a combined
switch and media player :)

-Toke
_______________________________________________
Cerowrt-devel mailing list
Cerowrt-devel@lists.bufferbloat.net
https://lists.bufferbloat.net/listinfo/cerowrt-devel



^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [Cerowrt-devel] expressobin
@ 2018-08-03 15:30 dpreed
  2018-08-03 22:55 ` Joel Wirāmu Pauling
  0 siblings, 1 reply; 10+ messages in thread
From: dpreed @ 2018-08-03 15:30 UTC (permalink / raw)
  To: Dave Taht
  Cc: Toke H&oslash,iland-J&oslash,rgensen, Daniel Ezell,
	Cake List, cerowrt-devel

https://www.cnx-software.com/2018/08/03/clearfog-gt-8k-high-end-networking-sbc-marvell-armada-a8040-processor/

Looks interesting... I like the SFP+ being there, too.

(Regarding Xilinx ... My focus is on the FPGA. The ARM cores are less interesting, other than that the FPGA side can directly access their cache system creating a powerful, fast, coherent autonomous DDR backed memory addressable memeory for packets that does not need processor intervention. But Xilinx parts are not cheap)




-----Original Message-----
From: "Dave Taht" <dave.taht@gmail.com>
Sent: Wed, Aug 1, 2018 at 4:06 pm
To: dpreed@deepplum.com
Cc: "Toke Høiland-Jørgensen" <toke@toke.dk>, "Daniel Ezell" <dezell@stonescry.com>, "Cake List" <cake@lists.bufferbloat.net>, cerowrt-devel@lists.bufferbloat.net
Subject: Re: Re: [Cerowrt-devel] expressobin

On Wed, Aug 1, 2018 at 5:49 AM dpreed@deepplum.com  wrote:
>
> Yeah. Small FF 2 port Celeron board is what I use. And I have a 4 port Atom that runs like a bat out of hell.
>
> Currenty fiddling with Xilinx Dev boards, just put packet processing in FPGA for Cake, and no problem with 2.5 - 10 Gb/sec. Just need a free piece of low level SFP+ interfacing logic.

cool. which? ultrascale?

I was looking over
http://cseweb.ucsd.edu/~ssradhak/Papers/senic-nsdi14.pdf again

> My use case is using the open ChipLink/TileLink bus from RISCV rather than PCIe, making something that might be an open source ASIC design.

How fast can that cpu context switch?

>
>
> -----Original Message-----
> From: "Toke Høiland-Jørgensen" 
> Sent: Wed, Aug 1, 2018 at 5:23 am
> To: "Dave Taht" , "Daniel Ezell" 
> Cc: "Dave Taht" , "Daniel Ezell" , "Cake List" , cerowrt-devel@lists.bufferbloat.net
> Subject: Re: [Cerowrt-devel] expressobin
>
> Dave Taht  writes:
>
> > It turns out it's just two ethernets with one, connected to a 2 port
> > switch. Not what I wanted. I'd wanted something different from the
> > apu2 or edgerouter X to play with, and I know the mvneta driver was
> > bql'd.
>
> I bought one of these to play with:
> https://teklager.se/en/products/routers/tlsense-i3-4lan
>
> x86 (i3 processor), four real ethernet ports, and passively cooled. A
> bit pricy, though; more than $400... But doubles well as a combined
> switch and media player :)
>
> -Toke
> _______________________________________________
> Cerowrt-devel mailing list
> Cerowrt-devel@lists.bufferbloat.net
> https://lists.bufferbloat.net/listinfo/cerowrt-devel
>
>


-- 

Dave Täht
CEO, TekLibre, LLC
http://www.teklibre.com
Tel: 1-669-226-2619



^ permalink raw reply	[flat|nested] 10+ messages in thread
* [Cerowrt-devel] expressobin
@ 2018-08-01  2:54 Dave Taht
  2018-08-01  3:05 ` Daniel Ezell
  2018-08-01 13:35 ` Mikael Abrahamsson
  0 siblings, 2 replies; 10+ messages in thread
From: Dave Taht @ 2018-08-01  2:54 UTC (permalink / raw)
  To: Cake List, cerowrt-devel

50 bucks. Dual core arm. 3 "real" ethernet ports?

https://www.amazon.com/Globalscale-Technologies-Inc-SBUD102-ESPRESSObin/dp/B06Y3V2FBK/ref=sr_1_1?ie=UTF8&qid=1491848966&sr=8-1&keywords=espressobin

with cake: https://github.com/davidk/espressobin-lede-sqm-cake


-- 

Dave Täht
CEO, TekLibre, LLC
http://www.teklibre.com
Tel: 1-669-226-2619

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-08-03 22:56 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-01 12:49 [Cerowrt-devel] expressobin dpreed
2018-08-01 12:56 ` Outback Dingo
2018-08-01 20:06 ` Dave Taht
  -- strict thread matches above, loose matches on Subject: below --
2018-08-03 15:30 dpreed
2018-08-03 22:55 ` Joel Wirāmu Pauling
2018-08-01  2:54 Dave Taht
2018-08-01  3:05 ` Daniel Ezell
2018-08-01  3:10   ` Dave Taht
2018-08-01  9:23     ` Toke Høiland-Jørgensen
2018-08-01 13:35 ` Mikael Abrahamsson

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