From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp85.iad3a.emailsrvr.com (smtp85.iad3a.emailsrvr.com [173.203.187.85]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 863AA3CB35; Fri, 1 Jan 2021 18:31:12 -0500 (EST) Received: from app52.wa-webapps.iad3a (relay-webapps.rsapps.net [172.27.255.140]) by smtp3.relay.iad3a.emailsrvr.com (SMTP Server) with ESMTP id 2994022FAC; Fri, 1 Jan 2021 18:31:12 -0500 (EST) Received: from deepplum.com (localhost.localdomain [127.0.0.1]) by app52.wa-webapps.iad3a (Postfix) with ESMTP id 14F11E0049; Fri, 1 Jan 2021 18:31:12 -0500 (EST) Received: by apps.rackspace.com (Authenticated sender: dpreed@deepplum.com, from: dpreed@deepplum.com) with HTTP; Fri, 1 Jan 2021 18:31:12 -0500 (EST) Date: Fri, 1 Jan 2021 18:31:12 -0500 (EST) From: "David P. Reed" To: "Dave Taht" Cc: "bloat" , "cerowrt-devel" , "Scott Manley" MIME-Version: 1.0 Content-Type: text/plain;charset=UTF-8 Content-Transfer-Encoding: quoted-printable Message-ID: <1609543872.082620517@apps.rackspace.com> X-Mailer: mobile/7.5.3 X-Classification-ID: 78086171-b742-415d-8d42-42480f25577c-1-1 Subject: Re: [Cerowrt-devel] =?utf-8?q?my_thx_to_spacex_=28and_kerbal_space_pr?= =?utf-8?q?ogram=29_forcheering_me_up_all_year?= X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Jan 2021 23:31:12 -0000 It has bufferbloat?=20 Why am I not surprised? I can share that one stack hasn't had it from the start, by design. That is= one implemented for trading at 10+ GB/sec, implemented in Verilog, and now= apparently in production use at one of the largest NY trading intermediari= es. Why? Simply two reasons: 1. People who design parallel hardware systems are trained to focus on clos= ing timing constraints. Which means never using FIFOs that are longer than = absolute minimum. The designer is a VLSI designer by trade, not a networkin= g guy. 2. Trading is all about managing delay. In this case, 100 msec packet delay= is worst allowable case end to end. Yet it is full TCP in hardware. Can't share more, because I don't know more, it being all proprietary to th= e bank in question. Now, one wonders: why can't Starlink get it right first time? It's not like bufferbloat is hard on a single bent pipe hop, which is all S= tarlink does today. -----Original Message----- From: "Dave Taht" Sent: Thu, Dec 31, 2020 at 1:37 pm To: "bloat" , "cerowrt-devel" , "Scott Manley" Cc: "bloat" , "cerowrt-devel" , "Scott Manley" Subject: [Cerowrt-devel] my thx to spacex (and kerbal space program) forche= ering me up all year If it wasn't for such a long list of wonderful accomplishments in space, it would have been a sadder year. i just re-recorded my song "one first landing" out on my dinghy: https://www.youtube.com/watch?v=3Dwjur0RG-v-I&feature=3Dyoutu.be Maybe someday I'll get scott manley to do his verse on this. Try as I might over the past few years, I still can't cop his accent. Now if we can only fix starlink's bufferbloat! It looks to me like the firmware is QCA's openwrt derivative... --=20 "For a successful technology, reality must take precedence over public relations, for Mother Nature cannot be fooled" - Richard Feynman dave@taht.net CTO, TekLibre, LLC Tel: 1-831-435-0729 _______________________________________________ Cerowrt-devel mailing list Cerowrt-devel@lists.bufferbloat.net https://lists.bufferbloat.net/listinfo/cerowrt-devel