From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp118.iad3a.emailsrvr.com (smtp118.iad3a.emailsrvr.com [173.203.187.118]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 19A5C3B29D for ; Tue, 2 Mar 2021 15:20:11 -0500 (EST) Received: from app16.wa-webapps.iad3a (relay-webapps.rsapps.net [172.27.255.140]) by smtp7.relay.iad3a.emailsrvr.com (SMTP Server) with ESMTP id 9123D4C39; Tue, 2 Mar 2021 15:20:10 -0500 (EST) Received: from deepplum.com (localhost.localdomain [127.0.0.1]) by app16.wa-webapps.iad3a (Postfix) with ESMTP id 7A1AE2004B; Tue, 2 Mar 2021 15:20:10 -0500 (EST) Received: by apps.rackspace.com (Authenticated sender: dpreed@deepplum.com, from: dpreed@deepplum.com) with HTTP; Tue, 2 Mar 2021 15:20:10 -0500 (EST) X-Auth-ID: dpreed@deepplum.com Date: Tue, 2 Mar 2021 15:20:10 -0500 (EST) From: "David P. Reed" To: "Dave Taht" Cc: "cerowrt-devel" MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_20210302152010000000_35816" Importance: Normal X-Priority: 3 (Normal) X-Type: html In-Reply-To: References: X-Client-IP: 209.6.10.161 Message-ID: <1614716410.497632160@apps.rackspace.com> X-Mailer: webmail/18.1.17-RC X-Classification-ID: 4e0dc1f3-d7d8-4204-89f6-153d8e436e09-1-1 Subject: Re: [Cerowrt-devel] easic from intel X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Mar 2021 20:20:11 -0000 ------=_20210302152010000000_35816 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =0AThese are ASICs, not fpgas. Presumably they are manufactured on Intel fa= bs using Intel processes, after designing them.=0A =0AThe overview referenc= es RTL design specs. Now Verilog and VHDL can speciry RTL designs (but are = a bit more general).=0A =0AAlso, the I/O pins seem to be a bit more special= ized than those of FPGAs I use from Xilinx. A typical FPGA has a fixed numb= er of specialized I/O pins that can do very fast SERDES, for example. But I= presume that these ASICs can have varying numbers of specialized I/O's.=0A= =0AWhat typically distinguishes FPGAs, MCUs and ASICs from general purpose= CPU chips is the I/O pins' potential configurability at design time. Gener= al purpose CPUs don't have GPIO or configurable specialized I/O. They typic= ally dedicate each pin to a particular electrical bus signaling physical la= yer.=0A =0AIn contrast, look at the STM32 or the RP2040 chips I/O pin specs= . Configurability from input to output to differential from voltage to volt= age on each single pin. These are things that software guys don't understan= d are important. And they aren't that important compared to logic and memor= y in general purpose CPUs like the X86 or the ARM general purpose chips.=0A= =0A =0AOn Monday, March 1, 2021 10:10pm, "Dave Taht" = said:=0A=0A=0A=0A> Got no idea how these really differ from fpgas. Do like= the number of=0A> gates tho. quad core 64bit arm also. Anyone seen the des= ign tools?=0A> =0A> https://www.intel.com/content/www/us/en/products/progra= mmable/asic/easic-devices/n5x.html=0A> =0A> --=0A> "For a successful techno= logy, reality must take precedence over public=0A> relations, for Mother Na= ture cannot be fooled" - Richard Feynman=0A> =0A> dave@taht.net CTO, TekLibre, LLC Tel: 1-831-435-0729=0A> _________________________= ______________________=0A> Cerowrt-devel mailing list=0A> Cerowrt-devel@lis= ts.bufferbloat.net=0A> https://lists.bufferbloat.net/listinfo/cerowrt-devel= =0A> ------=_20210302152010000000_35816 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

These are ASICs, not f= pgas. Presumably they are manufactured on Intel fabs using Intel processes,= after designing them.

=0A

 

=0A

The overview references RTL design specs. Now Verilog and VHDL can= speciry RTL designs (but are a bit more general).

=0A

 

=0A

Also, the I/O pins seem to be a bit mo= re specialized than those of FPGAs I use from Xilinx. A typical FPGA has a = fixed number of specialized I/O pins that can do very fast SERDES, for exam= ple. But I presume that these ASICs can have varying numbers of specialized= I/O's.

=0A

 

=0A

What t= ypically distinguishes FPGAs, MCUs and ASICs from general purpose CPU chips= is the I/O pins' potential configurability at design time. General purpose= CPUs don't have GPIO or configurable specialized I/O. They typically dedic= ate each pin to a particular electrical bus signaling physical layer.

= =0A

 

=0A

In contrast, look= at the STM32 or the RP2040 chips I/O pin specs. Configurability from input= to output to differential from voltage to voltage on each single pin. Thes= e are things that software guys don't understand are important. And they ar= en't that important compared to logic and memory in general purpose CPUs li= ke the X86 or the ARM general purpose chips.

=0A

&nb= sp;

=0A

 

=0A

On Monday,= March 1, 2021 10:10pm, "Dave Taht" <dave.taht@gmail.com> said:
=

=0A
=0A

> = Got no idea how these really differ from fpgas. Do like the number of
= > gates tho. quad core 64bit arm also. Anyone seen the design tools?
>
> https://www.intel.com/content/www/us/en/products/programm= able/asic/easic-devices/n5x.html
>
> --
> "For a s= uccessful technology, reality must take precedence over public
> re= lations, for Mother Nature cannot be fooled" - Richard Feynman
> > dave@taht.net <Dave T=C3=A4ht> CTO, TekLibre, LLC Tel: 1-831= -435-0729
> _______________________________________________
&g= t; Cerowrt-devel mailing list
> Cerowrt-devel@lists.bufferbloat.net=
> https://lists.bufferbloat.net/listinfo/cerowrt-devel
> <= /p>=0A

 ------=_20210302152010000000_35816--