From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ie0-x233.google.com (mail-ie0-x233.google.com [IPv6:2607:f8b0:4001:c03::233]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority" (verified OK)) by huchra.bufferbloat.net (Postfix) with ESMTPS id B424E21F182 for ; Sat, 20 Apr 2013 04:45:55 -0700 (PDT) Received: by mail-ie0-f179.google.com with SMTP id 16so5570900iea.24 for ; Sat, 20 Apr 2013 04:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:date:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=3QQEOZHLkHVY7uCmDXi/NfLMQstfK4mc1+4LgMdfVCY=; b=0vVsrEWv60685gKZq4I0AtbA/6d4YV0wx61bg11Jk1Q7VJe7/De3IZ0OP5+xrNv6EH a48CCjCVJQw6ml7DqyE12CoHfxwJzEQaHgIrNx5e0MQGHKOrbxkNrLCzVKHC0R8lM+9Z +j+zR98DXP70DiBmlYPAMunIs+dqq2bm6ssfuLTp/x8KrNX1hfYKkasGAhpXBtmdRXwc wuyyZW0aXzZUyvQ7dNAXWuteL50o4Ot40e+Et/4Gw2MrsvvnmZiOUkpqRZVi9K5vWrI1 i8xyG/L7MY/ImObjaDIaHQi+NNhcMNIcrGAgBNynIo5onB002ebU4O8V/QZsIeiUCDM7 Spdg== MIME-Version: 1.0 X-Received: by 10.50.6.34 with SMTP id x2mr10997255igx.86.1366458354994; Sat, 20 Apr 2013 04:45:54 -0700 (PDT) Received: by 10.64.132.71 with HTTP; Sat, 20 Apr 2013 04:45:54 -0700 (PDT) Date: Sat, 20 Apr 2013 04:45:54 -0700 Message-ID: From: Dave Taht To: cerowrt-devel@lists.bufferbloat.net Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: John Crispin Subject: [Cerowrt-devel] zynx chip/parallela thoughts X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 20 Apr 2013 11:45:55 -0000 The zynx-70X0 chip is looking increasingly attractive as a next generation router design target. Having the ability to write a better ethernet chip/switch, something that could talk gpon/fiber and eventually have well written in-hardware wireless interfaces is very appealing. I've been watching the xilinx kernel development tree and seeing things like full ethernet and PCIe master support land there, and blogic spent a bit of time coaxing openwrt to nearly boot up on a zedboard recently. But, it appears that all the existing dev boards don't do what I want, so designing a new PCB as a basic platform appears to be the starting place. Or finding someone that is designing one already to collaborate with... (?) Basically what would suit is 6 ethernet ports (macs and magnetics), + the ability to have 2 10gigE SFPs, a mini-pcie slot (to ease not having a near term wireless chip around), on-board flash (can live with a mini-sd card), 2 USB ports, and support for battery based operation.... The audio, video, and usb-otg ports on the existing zedboard could go. I don't see a whole lot of use for the plethora of switches and connectors on it either, obviously some LEDs are needed... Certainly being able to prototype SDR would be good too, but perhaps that would require retaining at least one FMC connector. I'm very encouraged by progress in the zynx-7020 parallela world, here's someone that's managed to boot gnu radio already: http://forums.parallella.org/viewtopic.php?f=3D20&t=3D265 And some pictures of the first manufactured boards that came out last week: http://www.parallella.org/2013/04/16/hello-world-my-name-is-parallella/ http://elinux.org/Parallella_Hardware :lust: (I've got one of these on order!) That's on the high end. On the low end I'm still seeking a decent atheros based board to continue building cero around. On Mon, Feb 4, 2013 at 8:41 AM, wrote: > I hadn't researched the HPC FMC requirement for 10 GigE one yet. > > > > The 1 GigE one is expensive, but not because of parts cost. This is the > usual huge markup that goes with stuff sold to "Design Engineers" in > companies - because they can charge, they do. > > > > The zedboard PMOD interface seems to be more marketing appropriate for > "cheap" stuff. There is a PMOD for 100baseT, so you could throw a few of > those on your system very cheaply. Since the interface to PMODs is 8-bi= t > parallel, all you might need is the magnetics and PHY for GigE, and you > could make a soft GigE controller in the programmable logic part of the > Zynq-7020. I'd have to check that the signalling rates would be sustaina= ble > across the PMOD connector. > > > > To make an FMC board, populate it with whatever GigE chip you like, etc. = is > trivial. It should cost no more to fabricate than one of these little > single chip GigE PCIe cards you can buy. What chip would you like to us= e? > I (or others) could design the board and BOM, kit it up for manufacturing > (by, say, Sunstone or other places that do PC boards and kitted assembly = in > small runs). > > > > Trivial stuff - maybe one could even convince Digilent and/or Avnet to do > the design/mfring. > > > > Wouldn't it be a lot better to have a pluggable and completely flexible > highly scalable monitoring unit that could go down the wire level as need= ed, > with the base cost being the $300 that a Zedboard goes from? > > > > And it would be completely "open hardware" and :"open source". > > > > -----Original Message----- > From: "Dave Taht" > Sent: Sunday, February 3, 2013 8:47pm > To: dpreed@reed.com > Cc: "Mark Constable" , cerowrt-devel@lists.bufferbloat.n= et > Subject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yurtlab > > Darn I wish I'd made it to that show today. > > On Sun, Feb 3, 2013 at 5:11 PM, wrote: >> >> http://www.prweb.com/releases/2012/2/prweb9154394.htm (10 GigE FMC card) >> >> > > > impressive. Seems to require a hpc (high pin count) board, which zed isn'= t. > >> >> >> http://www.xilinx.com/products/boards-and-kits/1-2AJPAV.htm (1 GiGE FMC >> card) > > > 625 eu. While I am painfully aware of how much it costs to step ahead of = the > bleeding edge, I think the odds are pointing harder and harder at doing a > non-fpga design that does what I want... > > I may go back to looking at octeons or ti's new octeon killer. > > And/or leveraging a newer atheros reference board. > >> >> >> >> >> -----Original Message----- >> From: "Dave Taht" >> Sent: Sunday, February 3, 2013 1:39pm >> To: dpreed@reed.com >> Cc: "Mark Constable" , >> cerowrt-devel@lists.bufferbloat.net >> Subject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yurtlab >> >> >> >> On Sun, Feb 3, 2013 at 10:26 AM, wrote: >>> >>> It would be trivial to do this with a Zedboard. >> >> >> Well, need two network ports. Haven't figured out much on interfacing th= e >> thing to offboard gear (I'd have liked it if it had a pci interface). So= is >> interfacing up a second network card "trivial" on the I/Os provided? >> >> And wanted esata, or some high speed disk I/O interface for captures. >> >> I'd rather like to continue forward on the zedboard front. The prospect = of >> designing an ethernet chip that actually could incorporate fq_codel etc = is >> very exciting. The RGII interface is available to access directly, in >> particular. >> >> >> >> >>> >>> >>> -----Original Message----- >>> From: "Dave Taht" >>> Sent: Sunday, February 3, 2013 1:17pm >>> To: "Mark Constable" >>> Cc: cerowrt-devel@lists.bufferbloat.net >>> Subject: Re: [Cerowrt-devel] stanford talk/deluged in hardware/yurtlab >>> >>> Well, I see it for 320. Then you need to add a SSD, and a decent networ= k >>> card, and I suppose it could be made to work. Awful big, tho, in an era >>> where I can get 1/2TB on an 2.5 inch SSD. >>> >>> What I'd wanted was closer to a dreamplug - 160 bucks, two network port= s, >>> but with an internal SSD. bonus points if it fit into a 1U rack and ate= as >>> little power as possible. >>> >>> Principal use case here is to be a "network monitor" with enough oomph = to >>> run stuff like cacti/mrtg/snmp tools, as well as do captures off of a >>> mirrored switch port. >>> >>> >>> >>> On Sun, Feb 3, 2013 at 10:10 AM, Dave Taht wrote: >>>> >>>> >>>> >>>> On Sun, Feb 3, 2013 at 10:03 AM, Mark Constable wrot= e: >>>>> >>>>> On 2013-02-03 09:18am, Dave Taht wrote: >>>>> > I'm grumpy, as it doesn't have an esata interface internally, >>>>> > apparently. >>>>> >>>>> https://www.google.com?q=3DHP+N40L+MicroServer >>>>> >>>>> I know this is no where near an embedded device but I just got one of >>>>> these >>>>> on sale (new model out) for $220 and I think it's the most useful >>>>> all-round >>>>> cheap server box I've ever seen. Some people have it running 16 GB ra= m >>>>> and >>>>> I've got mine booting off an SSD via external eSATA. Very well built >>>>> with 2 >>>>> x half height PCI slots (4 x eth port card?). Only missing USB3 ports >>>>> and >>>>> hot-swap drive space. And, very quiet with just an SSD. >>>> >>>> >>>> I'd be very interested to know how fast it could do packet header >>>> captures. >>>> >>>> Line rate (gigE) would be good. >>>> >>>> Does it do BQL? (what is the onboard ethernet chips) >>>> >>>> >>>> >>>> >>>>> >>>>> _______________________________________________ >>>>> Cerowrt-devel mailing list >>>>> Cerowrt-devel@lists.bufferbloat.net >>>>> https://lists.bufferbloat.net/listinfo/cerowrt-devel >>>> >>>> >>>> >>>> >>>> -- >>>> Dave T=E4ht >>>> >>>> Fixing bufferbloat with cerowrt: >>>> http://www.teklibre.com/cerowrt/subscribe.html >>> >>> >>> >>> >>> -- >>> Dave T=E4ht >>> >>> Fixing bufferbloat with cerowrt: >>> http://www.teklibre.com/cerowrt/subscribe.html >> >> >> >> >> -- >> Dave T=E4ht >> >> Fixing bufferbloat with cerowrt: >> http://www.teklibre.com/cerowrt/subscribe.html > > > > > -- > Dave T=E4ht > > Fixing bufferbloat with cerowrt: > http://www.teklibre.com/cerowrt/subscribe.html --=20 Dave T=E4ht Fixing bufferbloat with cerowrt: http://www.teklibre.com/cerowrt/subscribe.= html