[Cerowrt-devel] Fwd: [PATCH v2 2/2] igb: Make DMA faster when CPU is active on the PCIe link

[Dave Taht <dave.taht@gmail.com>]

I have sometimes wondered if it were possible to speed up the apu2 more.

---------- Forwarded message ---------
From: Kai-Heng Feng <kai.heng.feng@canonical.com>
Date: Wed, May 25, 2022 at 2:03 PM
Subject: [PATCH v2 2/2] igb: Make DMA faster when CPU is active on the PCIe link
To: <jesse.brandeburg@intel.com>, <anthony.l.nguyen@intel.com>
Cc: <mateusz.palczewski@intel.com>, Kai-Heng Feng
<kai.heng.feng@canonical.com>, David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>, Jeff Kirsher
<jeffrey.t.kirsher@intel.com>, Carolyn Wyborny
<carolyn.wyborny@intel.com>, <intel-wired-lan@lists.osuosl.org>,
<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>


Intel I210 on some Intel Alder Lake platforms can only achieve ~750Mbps
Tx speed via iperf. The RR2DCDELAY shows around 0x2xxx DMA delay, which
will be significantly lower when 1) ASPM is disabled or 2) SoC package
c-state stays above PC3. When the RR2DCDELAY is around 0x1xxx the Tx
speed can reach to ~950Mbps.

According to the I210 datasheet "8.26.1 PCIe Misc. Register - PCIEMISC",
"DMA Idle Indication" doesn't seem to tie to DMA coalesce anymore, so
set it to 1b for "DMA is considered idle when there is no Rx or Tx AND
when there are no TLPs indicating that CPU is active detected on the
PCIe link (such as the host executes CSR or Configuration register read
or write operation)" and performing Tx should also fall under "active
CPU on PCIe link" case.

In addition to that, commit b6e0c419f040 ("igb: Move DMA Coalescing init
code to separate function.") seems to wrongly changed from enabling
E1000_PCIEMISC_LX_DECISION to disabling it, also fix that.

Fixes: b6e0c419f040 ("igb: Move DMA Coalescing init code to separate function.")
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
---
 drivers/net/ethernet/intel/igb/igb_main.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/intel/igb/igb_main.c
b/drivers/net/ethernet/intel/igb/igb_main.c
index 68be2976f539f..c0d93fd19c1ed 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -9898,11 +9898,10 @@ static void igb_init_dmac(struct igb_adapter
*adapter, u32 pba)
        struct e1000_hw *hw = &adapter->hw;
        u32 dmac_thr;
        u16 hwm;
+       u32 reg;

        if (hw->mac.type > e1000_82580) {
                if (adapter->flags & IGB_FLAG_DMAC) {
-                       u32 reg;
-
                        /* force threshold to 0. */
                        wr32(E1000_DMCTXTH, 0);

@@ -9935,7 +9934,6 @@ static void igb_init_dmac(struct igb_adapter
*adapter, u32 pba)
                        /* Disable BMC-to-OS Watchdog Enable */
                        if (hw->mac.type != e1000_i354)
                                reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
-
                        wr32(E1000_DMACR, reg);

                        /* no lower threshold to disable
@@ -9952,12 +9950,12 @@ static void igb_init_dmac(struct igb_adapter
*adapter, u32 pba)
                         */
                        wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
                             (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
+               }

-                       /* make low power state decision controlled
-                        * by DMA coal
-                        */
+               if (hw->mac.type >= e1000_i210 ||
+                   (adapter->flags & IGB_FLAG_DMAC)) {
                        reg = rd32(E1000_PCIEMISC);
-                       reg &= ~E1000_PCIEMISC_LX_DECISION;
+                       reg |= E1000_PCIEMISC_LX_DECISION;
                        wr32(E1000_PCIEMISC, reg);
                } /* endif adapter->dmac is not disabled */
        } else if (hw->mac.type == e1000_82580) {
--
2.34.1



-- 
FQ World Domination pending: https://blog.cerowrt.org/post/state_of_fq_codel/
Dave Täht CEO, TekLibre, LLC