From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id D94F53B29E for ; Tue, 14 Jun 2022 12:00:43 -0400 (EDT) Received: by mail-ej1-x630.google.com with SMTP id n10so18076324ejk.5 for ; Tue, 14 Jun 2022 09:00:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :content-transfer-encoding; bh=/B5iTEUrm0VGN/zxFp2oDmBbHWd4FjoLzPoVQ2z2+qo=; b=I49QQroUinjBQth+7Sv/uLSrQOepdVcijZxd/WUJxazWSE8qcA67oQ8SHzBFOSya0G lfHSIZ8b8prmeY8vgtyNzJ6v1ECHhqtmxnmg1DVdJTrcxOi0m9ihiOGBK1MtADbaxwLz 6ZOK7U8+eb3jlNN0SjJ8didETcG7OG/jZJJlxZ0kJg68a0WA28I1CIXvQEqCHBUJziC4 OOiHkp3ekkSQ1lVTygHBi0N2VDbfmx5ICdKmN4QztFJ2rZJnHlZqT5kfKqLgXrBxCy0c VeOVeRjsCeJ3MC3KXSAyqswVzdeiK8rRVQMhhE73RNMOKcd6qqrlDTYNra3wUYBumxaF FhqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:content-transfer-encoding; bh=/B5iTEUrm0VGN/zxFp2oDmBbHWd4FjoLzPoVQ2z2+qo=; b=aDuDwZribTADk8I2DKIAHVnP6Rc+IHckvpNfmAQh7u2mx7XH+5YcVD8tmpaL9zQBd4 fX00dmBhve8qpx6h/ViHJXSrHJYuZhLYOxopx4TvccrLEOPg0u23uQqmEB1s5uv0MV02 D1tdV8YWLyG0cW3rAUqHDfR7cpIQooOw7M5jmIN9A3BOLv/dHIgeWVRCaEC96VAICDig UYT6SVUteY2G5ki2XJulK5vNbxMG/xDYgApodnQG5ucYdMYuGPjQXYzgGQrs93CZ4Ym0 T/Mg7fI2Gzv7ngntkPf46VlzJvtyMlQ1AKFeZTendXdrQMVa+ijZcgZgYJM7gF0U0/dj 65Ow== X-Gm-Message-State: AOAM531VTaS6ZtEfgjVytjfNEwzOyHYJMkoyQSeFlmpHR3o7VNGJLbd4 E2v6i1KlOh9829nFjS06vUxtsES4H5DIENmw9zHv5Q2N X-Google-Smtp-Source: ABdhPJxfM+Jxom3cVNyu2vVVUCJNz+dXXIWmI+F+AQ/fEd93FFGmixJnqkIIW4oFV9Lxok/1EPEqNbICV4OyNAuLebI= X-Received: by 2002:a17:906:2245:b0:715:7c81:e39d with SMTP id 5-20020a170906224500b007157c81e39dmr4908170ejr.262.1655222442457; Tue, 14 Jun 2022 09:00:42 -0700 (PDT) MIME-Version: 1.0 References: <20220525113113.171746-1-kai.heng.feng@canonical.com> <20220525113113.171746-2-kai.heng.feng@canonical.com> In-Reply-To: <20220525113113.171746-2-kai.heng.feng@canonical.com> From: Dave Taht Date: Tue, 14 Jun 2022 09:00:30 -0700 Message-ID: To: cerowrt-devel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Cerowrt-devel] Fwd: [PATCH v2 2/2] igb: Make DMA faster when CPU is active on the PCIe link X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jun 2022 16:00:44 -0000 I have sometimes wondered if it were possible to speed up the apu2 more. ---------- Forwarded message --------- From: Kai-Heng Feng Date: Wed, May 25, 2022 at 2:03 PM Subject: [PATCH v2 2/2] igb: Make DMA faster when CPU is active on the PCIe= link To: , Cc: , Kai-Heng Feng , David S. Miller , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jeff Kirsher , Carolyn Wyborny , , , Intel I210 on some Intel Alder Lake platforms can only achieve ~750Mbps Tx speed via iperf. The RR2DCDELAY shows around 0x2xxx DMA delay, which will be significantly lower when 1) ASPM is disabled or 2) SoC package c-state stays above PC3. When the RR2DCDELAY is around 0x1xxx the Tx speed can reach to ~950Mbps. According to the I210 datasheet "8.26.1 PCIe Misc. Register - PCIEMISC", "DMA Idle Indication" doesn't seem to tie to DMA coalesce anymore, so set it to 1b for "DMA is considered idle when there is no Rx or Tx AND when there are no TLPs indicating that CPU is active detected on the PCIe link (such as the host executes CSR or Configuration register read or write operation)" and performing Tx should also fall under "active CPU on PCIe link" case. In addition to that, commit b6e0c419f040 ("igb: Move DMA Coalescing init code to separate function.") seems to wrongly changed from enabling E1000_PCIEMISC_LX_DECISION to disabling it, also fix that. Fixes: b6e0c419f040 ("igb: Move DMA Coalescing init code to separate functi= on.") Signed-off-by: Kai-Heng Feng --- drivers/net/ethernet/intel/igb/igb_main.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index 68be2976f539f..c0d93fd19c1ed 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -9898,11 +9898,10 @@ static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) struct e1000_hw *hw =3D &adapter->hw; u32 dmac_thr; u16 hwm; + u32 reg; if (hw->mac.type > e1000_82580) { if (adapter->flags & IGB_FLAG_DMAC) { - u32 reg; - /* force threshold to 0. */ wr32(E1000_DMCTXTH, 0); @@ -9935,7 +9934,6 @@ static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) /* Disable BMC-to-OS Watchdog Enable */ if (hw->mac.type !=3D e1000_i354) reg &=3D ~E1000_DMACR_DC_BMC2OSW_EN; - wr32(E1000_DMACR, reg); /* no lower threshold to disable @@ -9952,12 +9950,12 @@ static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) */ wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - (IGB_TX_BUF_4096 + adapter->max_frame_size)) >= > 6); + } - /* make low power state decision controlled - * by DMA coal - */ + if (hw->mac.type >=3D e1000_i210 || + (adapter->flags & IGB_FLAG_DMAC)) { reg =3D rd32(E1000_PCIEMISC); - reg &=3D ~E1000_PCIEMISC_LX_DECISION; + reg |=3D E1000_PCIEMISC_LX_DECISION; wr32(E1000_PCIEMISC, reg); } /* endif adapter->dmac is not disabled */ } else if (hw->mac.type =3D=3D e1000_82580) { -- 2.34.1 --=20 FQ World Domination pending: https://blog.cerowrt.org/post/state_of_fq_code= l/ Dave T=C3=A4ht CEO, TekLibre, LLC