From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-il1-x12f.google.com (mail-il1-x12f.google.com [IPv6:2607:f8b0:4864:20::12f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 2197A3CB38 for ; Tue, 30 Nov 2021 19:33:49 -0500 (EST) Received: by mail-il1-x12f.google.com with SMTP id t8so23349910ilu.8 for ; Tue, 30 Nov 2021 16:33:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=R3LROym/S8alYFqDoZurv47TEqet9o/iXg1C8WiyKOw=; b=GH8L5v09GiHlxzyFFlPDAZ+dmU6eEqgJ9qKJ07NfOSW486lbWkyFiOnk0cpCNtPEFi ut3uSLyRUPHz+UrhxOJ0wTFrkeYZ4LLK+FNC3FfgLuM02durPhMa1L5gPwPhiOyeS0U8 WXUyXyabe1j/stzxgbpCkWUoQXwh4BArDw7TIlDzs6+EL8Gl778zq4HNWN6X6Cs1aozl VoVvXyQyYzCQnrftt6KHznkim06maV+0/NFexMjmeAlIGbKV4qcFIW7ceQ8kCW5hnNHt R2EFe1+0I8SzZXrLy0eOcPyqah8lfcAOIaH9vJXNjOOeOamQ6OPyXZCThtwdfdKIWZCX e9Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=R3LROym/S8alYFqDoZurv47TEqet9o/iXg1C8WiyKOw=; b=pw5srd4/3VsnRQLrKwZnRK+bHWNBfdzayHnDn4FFwSBHdTcI7nkxbxlW4AXvEAgvZR lvqUkwqpPDtgGSQNeX+BFuouhNgbOdzqE7QG5ZUOBM//CQKaVAxxs/225qAxwJKa3L/M iffZnGFNuxeWePGPZuSCpCnOMglJf1naE9tYbc+IZ2NafPer702xMGVZcyu7bSJjj9jP 92lxWQhosRrF931pAtl5xVMM+KoEyeWwwb238lFEmxZtyzIZKyopOWNxPHglxpwPiJwV BbXtbTprMjHHZYW71txYG0EQJEv690BkQKozdCUv/VxkxndriZpmam7Vh/1VPtrIxEb4 sEug== X-Gm-Message-State: AOAM530sho/LfZrtYAqLC7gH3an2Ujkf1yBaPKpPVKBhOy0RvHm3/d3Q ut6SUim3G6CKYLLaHoy9lgH/tTky6kGz5J6fdVo= X-Google-Smtp-Source: ABdhPJwSUcTckgAbWt8fR9PYxxSkbB5stFsxV7nM40Sx0DqbG7kYITB7W48yWjNE3Gri8E3rrJspSpko0bXUk9pHHyg= X-Received: by 2002:a05:6e02:16c9:: with SMTP id 9mr3350819ilx.221.1638318828437; Tue, 30 Nov 2021 16:33:48 -0800 (PST) MIME-Version: 1.0 References: <1638312755.776218387@apps.rackspace.com> In-Reply-To: From: Dave Taht Date: Tue, 30 Nov 2021 16:33:35 -0800 Message-ID: To: "David P. Reed" Cc: cerowrt-devel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Cerowrt-devel] risc-v options? X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Dec 2021 00:33:49 -0000 also, a 2.5ghz, 16 core chip was open sourced last month. https://www.cnx-software.com/2021/10/20/alibaba-open-source-risc-v-cores-xu= antie-e902-e906-c906-and-c910/ On Tue, Nov 30, 2021 at 4:23 PM Dave Taht wrote: > > On Tue, Nov 30, 2021 at 2:52 PM David P. Reed wrote= : > > > > For what? > > Because it's shiny. Because I don't care for the owner of softbank and > arm very much. Because at least the core is open source, and I'd > really like to try out some long held ideas about reducing context > switch latency. And there's a couple instructions I'd like to add. > > >I have recently gotten a MicroSemi RISC-V SoC board with embedded FPGA (= or maybe it is better thought of as an FPGA board with multicore hard logic= RISC-V host.) Runs Linux very fast. It's not set up to be a router, though= - not unless I populate its PCIe slot with NICs. Standard Linux drivers f= or PCIe devices all work quite well, so far. > > how fast can it context switch? (irtt bench) > > I am impressed that it works with anything on pcie. > > I was mostly dismissing risc-v as a toy that could never catch up to > arm 3 years ago, but with the enormous chinese investment in it... > > > > > > > These early 64 bit RISC-V implementations are pretty darn good, but unl= ike Intel's Xeons, they don't yet handle memory channel performance very we= ll. > > Intel has always had an advantage in on-chip cache. > > > > > > > > > (The 32-bit RISC-V's are really competing with ARM based microcontrolle= rs for embedded systems. I don't find them interesting, though I have a cou= ple sample boards with 32 bit RISC-V cores). > > I don't find 32 bit risc-v interesting. I did fiddle with the 128 bit > risc-v stuff for a while. > > > > > > > A random guess on my part: even consumer routers will be moving to 64-b= it processor designs in the next couple years. > > Many already have. > > > That's because the price difference is getting quite small, as a percen= tage of total product cost, and because it is hard to buy "small memory add= ress space" DIMMs. I could be wrong, but extrapolation from today's trends = suggests that is more likely than not. > > 802.11ax standards require - no joke - a 2MByte buffer per station. > > > > > > > > > > > > > On Friday, November 26, 2021 3:02pm, "Dave Taht" = said: > > > > > has anyone tried the latest generations of risc-v? > > > > > > https://linuxgizmos.com/17-sbc-runs-linux-on-allwinner-d1-risc-v-soc/ > > > > > > -- > > > I tried to build a better future, a few times: > > > https://wayforward.archive.org/?site=3Dhttps%3A%2F%2Fwww.icei.org > > > > > > Dave T=C3=A4ht CEO, TekLibre, LLC > > > _______________________________________________ > > > Cerowrt-devel mailing list > > > Cerowrt-devel@lists.bufferbloat.net > > > https://lists.bufferbloat.net/listinfo/cerowrt-devel > > > > > > > -- > I tried to build a better future, a few times: > https://wayforward.archive.org/?site=3Dhttps%3A%2F%2Fwww.icei.org > > Dave T=C3=A4ht CEO, TekLibre, LLC --=20 I tried to build a better future, a few times: https://wayforward.archive.org/?site=3Dhttps%3A%2F%2Fwww.icei.org Dave T=C3=A4ht CEO, TekLibre, LLC