From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io1-xd2a.google.com (mail-io1-xd2a.google.com [IPv6:2607:f8b0:4864:20::d2a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 001C23B29D for ; Tue, 2 Mar 2021 16:33:36 -0500 (EST) Received: by mail-io1-xd2a.google.com with SMTP id i8so23406343iog.7 for ; Tue, 02 Mar 2021 13:33:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=GUa/KQvqB07EIrRLQVC2QbnBiCN4dcrAn3fFaTFsZvY=; b=lckv+SoDAtAgWgRjghNxghkfIyx/qP010r8hDEGlswf3oPU3rM1tErfXuCocT3Aot6 qKFLDtfawAZkgnJp1HVfoFPSBs+DBIkhPyR46JGblz2tVEyCPT8XPIEQzrB8qmlAKdit KLcQXjjBUcnlnAEV4NUucdtAxvdjz33ouYO2O+4khU9f9HmXSQfm/9VZovK2xzm/gODA u2Gs5x/27AamdTsqE/FaXGH672jVbIO6d1ic9Ht1sDOZ4SRNgVIPdQo9ZuPGyBEPMgmc nXKmo07CCKYosv7mH5u6DN0pNrsBaisXXWAYmgBhMUE4oZ9dZjos7kD4Oz8RpJ7vbQfA HPGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=GUa/KQvqB07EIrRLQVC2QbnBiCN4dcrAn3fFaTFsZvY=; b=Lusczg6/EE1tGmJ90+rdaT53SoOTJfxCAoXNL0ziRHfTcyLLjCzhN7off/D7FgW6Hf +O1pz0qkmKnIt5/tpuOv+F+sEw/rZbgXpwCZqQw7Lx6V163ncuzPkHOvyZzMjKfCJ5eg QROtjTldUodpNIR9k5ifBPeLMZv9TJqZ16PRXvFUNmRopkpu3hD4l32zew6TNLRWaakN 9Wdkv6Ge3qpvyDLmduN4VZ/32DuHu4r+J9phhel8ohEiTCkn388PaARqBMXMYSMXWkD1 DZ0c/p3t0Y0ygWX7qFLfJXsdfinNyJbW61ezD0KN9pxc1XWlhKQ9wQ2uVP+YTtRDKJS2 iz8A== X-Gm-Message-State: AOAM531I4WLt2shXDJ6FuhE1+Nxp1D6pGu5qO9fgsjfafFE0KNDQyhj/ zNW/F2Opn90/J5/RyG1Q1MH3btZNXrqEuXMI1YsC3dBypbs= X-Google-Smtp-Source: ABdhPJzjQq/+69XZZhKu119HZ4+q3h6jhVTsrR7s5Y3lRDPDCi3YUNRBBUQw5jwPKRbqq2Eas8OuxpgkKJ56ZzV+YR8= X-Received: by 2002:a6b:6618:: with SMTP id a24mr7685217ioc.100.1614720816450; Tue, 02 Mar 2021 13:33:36 -0800 (PST) MIME-Version: 1.0 References: <1614716410.497632160@apps.rackspace.com> In-Reply-To: <1614716410.497632160@apps.rackspace.com> From: Dave Taht Date: Tue, 2 Mar 2021 13:33:25 -0800 Message-ID: To: "David P. Reed" Cc: cerowrt-devel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Cerowrt-devel] easic from intel X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Mar 2021 21:33:37 -0000 My own deep desire is to somehow achieve very high framerate video, on a 2ms boundary (eg, 500 frames/sec). Scan line style output is fine, but some level of scan line compression probably helpful. Getting that right is the last major requirement to finally build my old jamaphone concept. 16ms frames suck, current encodings suck worse. On Tue, Mar 2, 2021 at 12:20 PM David P. Reed wrote: > > These are ASICs, not fpgas. Presumably they are manufactured on Intel fab= s using Intel processes, after designing them. > > > > The overview references RTL design specs. Now Verilog and VHDL can specir= y RTL designs (but are a bit more general). > > > > Also, the I/O pins seem to be a bit more specialized than those of FPGAs = I use from Xilinx. A typical FPGA has a fixed number of specialized I/O pin= s that can do very fast SERDES, for example. But I presume that these ASICs= can have varying numbers of specialized I/O's. > > > > What typically distinguishes FPGAs, MCUs and ASICs from general purpose C= PU chips is the I/O pins' potential configurability at design time. General= purpose CPUs don't have GPIO or configurable specialized I/O. They typical= ly dedicate each pin to a particular electrical bus signaling physical laye= r. > > > > In contrast, look at the STM32 or the RP2040 chips I/O pin specs. Configu= rability from input to output to differential from voltage to voltage on ea= ch single pin. These are things that software guys don't understand are imp= ortant. And they aren't that important compared to logic and memory in gene= ral purpose CPUs like the X86 or the ARM general purpose chips. > > > > > > On Monday, March 1, 2021 10:10pm, "Dave Taht" said: > > > Got no idea how these really differ from fpgas. Do like the number of > > gates tho. quad core 64bit arm also. Anyone seen the design tools? > > > > https://www.intel.com/content/www/us/en/products/programmable/asic/easi= c-devices/n5x.html > > > > -- > > "For a successful technology, reality must take precedence over public > > relations, for Mother Nature cannot be fooled" - Richard Feynman > > > > dave@taht.net CTO, TekLibre, LLC Tel: 1-831-435-0729 > > _______________________________________________ > > Cerowrt-devel mailing list > > Cerowrt-devel@lists.bufferbloat.net > > https://lists.bufferbloat.net/listinfo/cerowrt-devel > > --=20 "For a successful technology, reality must take precedence over public relations, for Mother Nature cannot be fooled" - Richard Feynman dave@taht.net CTO, TekLibre, LLC Tel: 1-831-435-0729