From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-bk0-f49.google.com (mail-bk0-f49.google.com [209.85.214.49]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority" (verified OK)) by huchra.bufferbloat.net (Postfix) with ESMTPS id A91E921F18C; Thu, 20 Dec 2012 00:27:13 -0800 (PST) Received: by mail-bk0-f49.google.com with SMTP id jm19so1477886bkc.36 for ; Thu, 20 Dec 2012 00:27:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=986kKaE8RGN4gjk7JiPkBoNNaySr7r+Cj3g7q8f2dOA=; b=JFoOjPy2EbGNkq5wrTqmVFxh/ztIINxNOa6JohvHGu8YVsUIosoXlNj0aY8ZHV9vZn gck7H2e51yVsSZj4HB2Id3SOgI3m+4wWcjeOKJRZAPSK1p1PNYwM9hJaS8FTztFX7uSh QIld5Hdkl3ths+4Xa/gIvlSs5TuSpkzHZ0xfS/G8AO/IqOlKCWGTVOja9NnBzYFdiO1b FDOc4fUJwawlUZ1cwVkI6RZ9hPzJV1Mn0CYTfb2zbNOD2WIfdpVVRkYtGlfD1ZHCTF0B E1nQwZLcUwiFmJfMLWXay7ep9xaF60cmtp99ux+OfEQ5biUlP+eKTXfqWyN8TUgHgAHC 0hzQ== MIME-Version: 1.0 Received: by 10.205.120.3 with SMTP id fw3mr4237136bkc.40.1355992031488; Thu, 20 Dec 2012 00:27:11 -0800 (PST) Received: by 10.204.36.138 with HTTP; Thu, 20 Dec 2012 00:27:11 -0800 (PST) Received: by 10.204.36.138 with HTTP; Thu, 20 Dec 2012 00:27:11 -0800 (PST) In-Reply-To: <20121220081737.1A681800037@ip-64-139-1-69.sjc.megapath.net> References: <20121220081737.1A681800037@ip-64-139-1-69.sjc.megapath.net> Date: Thu, 20 Dec 2012 10:27:11 +0200 Message-ID: From: Jonathan Morton To: Hal Murray Content-Type: multipart/alternative; boundary=001517475cb05aec1604d1447f15 Cc: bloat-devel , codel@lists.bufferbloat.net, cerowrt-devel@lists.bufferbloat.net Subject: Re: [Cerowrt-devel] hardware hacking on fq_codel in FPGA form at 10GigE X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Dec 2012 08:27:14 -0000 --001517475cb05aec1604d1447f15 Content-Type: text/plain; charset=ISO-8859-1 A small CPU can be made in perhaps 35K gates - something like an ARM7TDMI or a Cortex-M0. It is common to stick one of those in a special purpose chip to help with control logic. But that would operate at a few hundred MHz, which leaves only a few cycles per packet for small packets. That's not enough to run even a relatively simple algorithm like codel. Dedicated logic that *is* fast enough to run the algorithm on each packet shouldn't be any bigger than such a CPU. - Jonathan Morton On Dec 20, 2012 10:17 AM, "Hal Murray" wrote: > > If I was going to do something like that, I'd build a small/simple CPU and > do > the work in microcode. > > > implementing {n,e,s}fq_codel onboard looks very feasible > > How many lines of assembler code would it take? > > How many registers do you need? Do you need any memory other than queues? > Maybe counters? > > > > The only thing that is seriously serial about fq_codel is shooting the > > biggest flow when the queue limit is exceeded, and that could be made > > embarrassingly parallel with enough gates.There are no doubt other tricky > > issues. > > Would it be better to do the fq work in the main CPU and let the FPGA grab > packets from some shared data structure in memory? Can you work out a > memory structure that doesn't need locks? > > > -- > These are my opinions. I hate spam. > > > > _______________________________________________ > Bloat-devel mailing list > Bloat-devel@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/bloat-devel > --001517475cb05aec1604d1447f15 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

A small CPU can be made in perhaps 35K gates - something like an ARM7TDM= I or a Cortex-M0. It is common to stick one of those in a special purpose c= hip to help with control logic.

But that would operate at a few hundred MHz, which leaves only a few cyc= les per packet for small packets. That's not enough to run even a relat= ively simple algorithm like codel.

Dedicated logic that *is* fast enough to run the algorithm on each packe= t shouldn't be any bigger than such a CPU.

- Jonathan Morton

On Dec 20, 2012 10:17 AM, "Hal Murray"= <hmurray@megapathdsl.net= > wrote:

If I was going to do something like that, I'd build a small/simple CPU = and do
the work in microcode.

> implementing {n,e,s}fq_codel onboard looks very feasible

How many lines of assembler code would it take?

How many registers do you need? =A0Do you need any memory other than queues= ?
Maybe counters?


> The only thing that is seriously serial about fq_codel is shooting the=
> biggest flow when the queue limit is exceeded, and that could be made<= br> > embarrassingly parallel with enough gates.There are no doubt other tri= cky
> issues.

Would it be better to do the fq work in the main CPU and let the FPGA grab<= br> packets from some shared =A0data structure in memory? =A0Can you work out a=
memory structure that doesn't need locks?


--
These are my opinions. =A0I hate spam.



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