From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp145.dfw.emailsrvr.com (smtp145.dfw.emailsrvr.com [67.192.241.145]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by huchra.bufferbloat.net (Postfix) with ESMTPS id 7953921F549 for ; Sat, 13 Dec 2014 15:02:31 -0800 (PST) Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp11.relay.dfw1a.emailsrvr.com (SMTP Server) with ESMTP id F141C2801B8; Sat, 13 Dec 2014 18:02:30 -0500 (EST) X-Virus-Scanned: OK Received: by smtp11.relay.dfw1a.emailsrvr.com (Authenticated sender: dpreed-AT-reed.com) with ESMTPSA id 0BCCB2801B9; Sat, 13 Dec 2014 18:02:29 -0500 (EST) X-Sender-Id: dpreed@reed.com Received: from [100.65.200.128] (177.sub-70-192-36.myvzw.com [70.192.36.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA) by 0.0.0.0:465 (trex/5.4.2); Sat, 13 Dec 2014 23:02:30 GMT User-Agent: K-@ Mail for Android X-Priority: 3 In-Reply-To: References: <548A9A66.1040002@iki.fi> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----4I49K11I51QZR9AJGQE1GELBOPZDT2" Content-Transfer-Encoding: 7bit From: "David P. Reed" Date: Sat, 13 Dec 2014 18:02:25 -0500 To: "Mike \"dave\" Taht" , Erkki Lintunen Message-ID: Cc: "cerowrt-devel@lists.bufferbloat.net" Subject: Re: [Cerowrt-devel] an option for a new platform? X-BeenThere: cerowrt-devel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: Development issues regarding the cerowrt test router project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 13 Dec 2014 23:03:00 -0000 ------4I49K11I51QZR9AJGQE1GELBOPZDT2 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Anyone measured what is the actual bottleneck in 300 mb/s shaping? On an I= ntel platform you can measure a running piece of code pretty accurately=2E = I ask because it is not obvious a cpu needs to touch much of a frame to do = shaping, so it seems more likely that the driver and memory management stru= ctures are the bottleneck=2E But it is really easy to write very slow code= in a machine with limited cache=2E So maybe that is it=2E On a multi cor= e intel arch machine these days it is a surprising fact that a single core = can't use up more than about 25 percent of a socket's memory cycles so to = get full i/o speed you need to be running your code on 4 cores or more=2E= =2E=2E this kind of thing can really limit achievable speed of a poorly thr= eaded design=2E Architectural optimization needs more than llvm and clean = code=2E You need to think about the whole software pipeline=2E Debian may n= ot be great out of the box for this reason - it was never designed for rout= ing throughput=2E On Dec 12, 2014, Dave Taht wro= te: >There was a review of that hardware that showed it couldn't push more = >than 600Mbit natively (without shaping)=2E I felt that the ethernet >drive= r could be improved significantly after looking it over, but >didn't care f= or the 600mbit as a starting point to have to improve >from=2E > >Not rulin= g it out, though! It met quite a few requirements we have=2E > >On Thu, Dec= 11, 2014 at 11:33 PM, Erkki Lintunen >wrote: >> >> Hell= o, >> >> while enjoying and reading another thread from the list=2E=2E=2E >= > >>> -------- Forwarded Message -------- >>> Subject: Re: [Cerowrt-devel] = how is everyone's uptime? >>> Date: Thu, 11 Dec 2014 16:42:37 -0800 >>> Fro= m: Dave Taht >> [snip] >>> But frankly, I would p= refer for most of the chaos there to subside >and to find >>> a new, additi= onal platform, to be working on before resuming work, >>> that can do inbou= nd shaping at up to 300mbit=2E And >>> to be more openwrt compatible in wha= tever we do, whatever that is=2E >> >> this reminded me that another day I = passed a web-page of a platform >and >> in the hope this has not been on th= e list yet passing it forward=2E >> >> >> >> An interesting tidbit in the platform is the choice of firmware, = I >> think=2E Haven't seen any board yet with the similar choice by the >> = manufacturer=2E With a quick summing from the vendor part catalog, the >> p= latform is sub 200 EUR (238 USD in current exchange rate) for an >about >> = working assembly of 3x 1GbE, 4G ram, 1G flash, 802=2E11a/b/g/n radio=2E=2E= =2E >> >> I can't say anything how capable the hw might be for the stated >= inbound >> shaping performance=2E I have had an ALIX board from their previ= ous >> generation for years and its been humming nicely though I haven't >p= ushed >> it to its envelope=2E >> >> Best >> Erkki >> _____________________= __________________________ >> Cerowrt-devel mailing list >> Cerowrt-devel@l= ists=2Ebufferbloat=2Enet >> https://lists=2Ebufferbloat=2Enet/listinfo/cero= wrt-devel > > > >-- >Dave T=C3=A4ht > >thttp://www=2Ebufferbloat=2Enet/pro= jects/bloat/wiki/Upcoming_Talks >__________________________________________= _____ >Cerowrt-devel mailing list >Cerowrt-devel@lists=2Ebufferbloat=2Enet = >https://lists=2Ebufferbloat=2Enet/listinfo/cerowrt-devel -- Sent from my = Android device with K-@ Mail=2E Please excuse my brevity=2E ------4I49K11I51QZR9AJGQE1GELBOPZDT2 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable Anyone measured what is the actual bottleneck in 3= 00 mb/s shaping?  On an Intel platform you can measure a running piece= of code pretty accurately=2E I ask because it is not obvious a cpu needs t= o touch much of a frame to do shaping, so it seems more likely that the dri= ver and memory management structures are the bottleneck=2E

But it is really easy to write very slow code in a m= achine with limited cache=2E So maybe that is it=2E
On a multi core intel arch machine these days i= t is a surprising fact that a single core can't use up more than about 25 p= ercent of  a socket's memory cycles so to get full i/o speed you need = to be running your code on 4 cores or more=2E=2E=2E this kind of thing can = really limit achievable speed of a poorly threaded design=2E  Architec= tural optimization needs more than llvm and clean code=2E You need to think= about the whole software pipeline=2E Debian may not be great out of the bo= x for this reason - it was never designed for routing throughput=2E

On Dec 12, 2014, D= ave Taht <dave=2Etaht@gmail=2Ecom> wrote:
There was a review =
of that hardware that showed it couldn't push more
than 6=
00Mbit natively (without shaping)=2E I felt that the ethernet
driver could be improved significantly after looking it over, but
didn't care for the 600mbit as a starting point to have to im=
prove
from=2E

Not ru=
ling it out, though! It met quite a few requirements we have=2E

On Thu, Dec 11, 2014 at 11:33 PM, Erkki Lintunen =
<ebirdie@iki=2Efi> wrote:

=
Hello,
<= br clear=3D"none">while enjoying and reading another thread from the list= =2E=2E=2E

-------- Forwarded Message --------
= Subject: Re: [Cerowrt-devel] how is everyone's uptime?
Da= te: Thu, 11 Dec 2014 16:42:37 -0800
From: Dave Taht <d= ave=2Etaht@gmail=2Ecom>
[snip]
But frankly, I = would prefer for most of the chaos there to subside and to find
a new, additional platform, to be working on before resuming work,that can do inbound shaping at up to 300mbit=2E And
to be more openwrt compatible in whatever we do, whatever that = is=2E

this reminded me that another day I pa= ssed a web-page of a platform and
in the hope this has no= t been on the list yet passing it forward=2E

<http://www=2Epcengines=2Ech/apu=2Ehtm>

An interesting tidbit in the platform is the choice of firmware, = I
think=2E Haven't seen any board yet with the similar ch= oice by the
manufacturer=2E With a quick summing from the= vendor part catalog, the
platform is sub 200 EUR (238 US= D in current exchange rate) for an about
working assembly= of 3x 1GbE, 4G ram, 1G flash, 802=2E11a/b/g/n radio=2E=2E=2E

I can't say anything how capable the hw might be fo= r the stated inbound
shaping performance=2E I have had an= ALIX board from their previous
generation for years and = its been humming nicely though I haven't pushed
it to its= envelope=2E

Best
Er= kki

Cerowrt-devel mailing list
Cerowrt-devel@lists=2Ebufferbloat=2Enet
https://lists=2Ebufferbloat=2Enet/listinfo/cerowrt-devel


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