From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ip-64-139-1-69.sjc.megapath.net (ip-64-139-1-69.sjc.megapath.net [64.139.1.69]) by huchra.bufferbloat.net (Postfix) with ESMTP id AA43E21F17D; Thu, 20 Dec 2012 00:17:37 -0800 (PST) Received: from shuksan (localhost [127.0.0.1]) by ip-64-139-1-69.sjc.megapath.net (Postfix) with ESMTP id 1A681800037; Thu, 20 Dec 2012 00:17:37 -0800 (PST) X-Mailer: exmh version 2.7.2 01/07/2005 with nmh-1.3 To: Dave Taht From: Hal Murray In-Reply-To: Message from Dave Taht of "Thu, 20 Dec 2012 02:28:19 EST." Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 20 Dec 2012 00:17:37 -0800 Message-Id: <20121220081737.1A681800037@ip-64-139-1-69.sjc.megapath.net> X-Mailman-Approved-At: Thu, 20 Dec 2012 01:27:40 -0800 Cc: codel@lists.bufferbloat.net, hmurray@megapathdsl.net, bloat-devel , cerowrt-devel@lists.bufferbloat.net Subject: Re: [Codel] hardware hacking on fq_codel in FPGA form at 10GigE X-BeenThere: codel@lists.bufferbloat.net X-Mailman-Version: 2.1.13 Precedence: list List-Id: CoDel AQM discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Dec 2012 08:17:38 -0000 If I was going to do something like that, I'd build a small/simple CPU and do the work in microcode. > implementing {n,e,s}fq_codel onboard looks very feasible How many lines of assembler code would it take? How many registers do you need? Do you need any memory other than queues? Maybe counters? > The only thing that is seriously serial about fq_codel is shooting the > biggest flow when the queue limit is exceeded, and that could be made > embarrassingly parallel with enough gates.There are no doubt other tricky > issues. Would it be better to do the fq work in the main CPU and let the FPGA grab packets from some shared data structure in memory? Can you work out a memory structure that doesn't need locks? -- These are my opinions. I hate spam.