From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail2.candelatech.com (mail2.candelatech.com [208.74.158.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 7A9713B2AB; Wed, 30 Mar 2016 11:28:38 -0400 (EDT) Received: from [192.168.100.149] (firewall.candelatech.com [50.251.239.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail2.candelatech.com (Postfix) with ESMTPSA id D1D1A40EB43; Wed, 30 Mar 2016 08:28:36 -0700 (PDT) To: Michal Kazior References: <1458898743-21118-1-git-send-email-michal.kazior@tieto.com> <56FAA518.2000805@candelatech.com> Cc: Dave Taht , "ath10k@lists.infradead.org" , linux-wireless , make-wifi-fast@lists.bufferbloat.net, "codel@lists.bufferbloat.net" From: Ben Greear Organization: Candela Technologies Message-ID: <56FBF0A4.5090508@candelatech.com> Date: Wed, 30 Mar 2016 08:28:36 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Codel] [RFC] ath10k: implement dql for htt tx X-BeenThere: codel@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: CoDel AQM discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Mar 2016 15:28:38 -0000 On 03/30/2016 02:22 AM, Michal Kazior wrote: > On 29 March 2016 at 17:54, Ben Greear wrote: >> On 03/29/2016 12:49 AM, Michal Kazior wrote: >> >>>> if you are getting a pure codel result of 160ms, that means the >>>> implementation is broken. But I think (after having read your >>>> description twice), the baseline result today of 160ms of queuing was >>>> with a fq_codel *qdisc* doing the work on top of huge buffers, >>> >>> >>> Yes. The 160ms is with fq_codel qdisc with ath10k doing DQL at 6mbps. >>> Without DQL ath10k would clog up all tx slots (1424 of them) with >>> frames. At 6mbps you typically want/need a handful (5-10) of frames to >>> be queued. >> >> >> Have you actually verified you can use all tx slots? > > It works in most cases. I guess you're suspecting some of your > tx(flushing?) problems might be induced by overcommiting? > >> The way the >> firmware uses it's tx buffers I think you may not be able to actually >> do that...and in practice, you will get a lot fewer usable tx-buffers >> than configured.... > > Could be, e.g. I'm aware management frames are kind of a special case > in recent firmware revisions. > > What would/do you expect firmware would/will do when we overcommit? > The driver does advertise number of HTT tx slots so I would expect it > to work fine if it didn't crash during boot. The firmware will return something like tx-dropped immediately. The reason is that the firmware keeps more than one internal priority queue, and in general, reserves some of the tx-descriptors for high priority. So, you never see tx-queues completely full in the driver, so tx queues are not stopped farther up the stack. Possibly I am confused about some of this, so I'm quite curious if you ever see tx-queues determined to be full in the ath10k driver. Thanks, Ben -- Ben Greear Candela Technologies Inc http://www.candelatech.com