What are you expecting from chip makers? HW ASIC guys are rarely good at writing sw and not so good at systems either. SW tends to be small, high velocity teams that make a lot of mistakes through iterations. Some get addicted to the velocity. ASICs tend to be low thousands of engineers paying attention to a plethora of details like signal integrity to get a $30M-50M mask right before spending another $100M+ for a run of millions. Completely different operating models. It's like comparing a container ship to a NASA X-43.
Bob
PS. I think we're missing EDCA analysis which is a BSS manager and AP thing. The default values really aren't optimized for anything and just are example settings. We also need active redundancy. Lots to be done still from what I can tell.
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