[Bloat] First draft of complete "Bufferbloat And You" enclosed.

[richard]

On Tue, 2011-02-08 at 13:18 -0500, Eric Raymond wrote:
> Justin McCann <jneilm at gmail.com>:
> > This may be intentional, but the text launches into an explanation of
> > why bufferbloat is bad without concisely explaining what it is--- you
> > have to read the whole first two sections before it's very clear.
> 
> Not intentional, exactly, but's inherent.  Thec reader *can't* get what
> bufferbloat.
> 
> > The second of the three main tactics states, "Second, we can decrease
> > buffer sizes.  This cuts the delay due to latency and decreases the
> > clumping effect on the traffic." Latency *is* delay; perhaps "cuts the
> > delay due to buffering" or "due to queueing" would be better, if more
> > tech-ese.
> 
> Good catch, I'll fix.
>  
> > I've re-read through the Bell Labs talk, and some of the earlier
> > posts, but could someone explain the "clumping" effect? I understand
> > the wild variations in congestion windows ("swing[ing] rapidly and
> > crazily between emptiness and overload"), but clumping makes me think
> > of closely spaced packet intervals.
> 
> It's intended to.  This is what I got from jg's talk, and I wrote the
> SOQU scenario to illustrate it. If my understanding is incorrect (and
> I see that you are saying it is) one of the real networking people
> here needs to whack me with the enlightenment stick.
> 
> The underlying image in my just-so stories about roads and parking lots
> is that packet flow coming in smooth on the upstream side of a buffwer
> gets turned into a buffer fill, followed by a burst of packets as it 
> overflows, followed by more data coming into the buffer, followed by
> overflow...repeat.

My electronics (analog, tube, etc.) background makes me view a lot of
this as "tuned" circuits - capacitors, resistors, coils, etc.

If I read things correctly, there are a number of different ways buffers
are used/abused. They're all FIFO (I hope - somebody disabuse me of this
idea if they have evidence) but how they deal with high/low water marks
seems to make a difference.

Actual processor capabilities (and overall system load) may also play a
role - the embedded stack processor and/or the system's CPU including
things like interrupt load, bus mastering, DMA, etc.

If the interface is capable of full bandwidth in and out at the same
time, and high/low water mark detection is quick, then I'd think this is
a circuit that has little tendency to oscillate at any low, detectable
frequency.

If the interface is not capable of full bandwidth in and out at the same
time, and/or the detection of or settings for high/low water mark in the
buffer are screwy, then the system will oscillate at a low frequency and
you'll get clumping.

I'd expect to see this on cheap Gbit Ethernet cards on PCI bus (lots of
interrupts to the main CPU) as the system's load rises for example; one
of the reasons I've stopped using them, even on lightly loaded links.

richard

-- 
Richard C. Pitt                 Pacific Data Capture
rcpitt at pacdat.net               604-644-9265
http://digital-rag.com          www.pacdat.net
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