[Bloat] Fwd: [NetFPGA-nf10g-announce] NetFPGA Design Challenge 2017
dave.taht at gmail.com
Thu Nov 17 10:30:08 EST 2016
---------- Forwarded message ----------
From: Noa Zilberman <noa.zilberman at cl.cam.ac.uk>
Date: Wed, Nov 16, 2016 at 8:17 AM
Subject: [NetFPGA-nf10g-announce] NetFPGA Design Challenge 2017
To: cl-netfpga-announce at lists.cam.ac.uk
We are pleased to announce the 2017 NetFPGA Design Challenge!
The NetFPGA 2017 contest has one design challenge. The design teams have
150 days to produce a working implementation employing any HW and SW design
methodology and targeting the NetFPGA SUME platform. The contest begins on
November 16th, 2016. The winners will be announced at the NetFPGA
Developers Summit (Thursday 20th - Friday, 21st April, 2017 Cambridge, UK).
*Challenge: Lowest Latency Switch*
Low latency devices are being increasingly used across a large number of
applications. Low latency solutions are few, and are rarely open source.
The goal of this challenge is to provide a usable, high performance, open
source alternative to use by universities and organizations who need the
flexibility of open source.
The systems will be evaluated using OSNT, an Open Source Network Tester.
Test benches will be available online, for users to experiment and
independently evaluate their design.
The competition is open to students of all levels (undergraduate and
postgraduate), as well as to non students. There is no need to own a
NetFPGA SUME platform to take part in the competition.
More details can be found at:
The NetFPGA Team
cl-netfpga-announce mailing list
cl-netfpga-announce at lists.cam.ac.uk
Let's go make home routers and wifi faster! With better software!
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