On Sun, 26 Aug 2018, Dave Taht wrote: > I was on that thread. It was broken before entirely. As for the single > interrupt on this chip variant - believe it or not, I'm not huge on When doing 10GE tests on x86-64 I received the highest performance when I set interrupt affinity to single core per interface. -- Mikael Abrahamsson email: swmike at swm.pp.se