[Bloat] 400g Tomahawk-3 chip

[Jonathan Morton]

> On 27 Jan, 2018, at 5:31 am, Dave Taht <dave.taht at gmail.com> wrote:
> 
> If someone could translate the "smart buffering", "flow aware" and
> "mice v elephants" comments into how it actually works in the
> tomahawk-3 chip... I'd love it.

Just reading what you quoted, it looks like they have a big buffer which can absorb incast bursts effectively (that is, without incurring burst loss), but they also have flow isolation to minimise the inter-flow induced latency that a large buffer would normally imply.  That's definitely a step forward if it's actually in the hardware at those sorts of speeds.

Precisely what counts as "a flow" is not quite clear.  It could be just IP address pairs, rather than 5-tuples.

There doesn't seem to be any explicit mention of AQM here, but that reference to RoCEv2 "congestion control" might imply something in that category - or it could just be a back-pressure mechanism to hint local applications.

 - Jonathan Morton