[Bloat] known buffer sizes on switches

[Dave Taht]

I really don't know a whole heck of a lot about where mips is going.
Certainly they remain strong in the embedded market (I do like the
edgerouter X a lot), but as for their current direction or future
product lines, not a clue.

I used to know someone over there, maybe he's restored new directions.
Last I recall he was busy obsoleting a whole lot of instruction space
in order to make room for "new stuff". He'd even asked me if adding an
invsqrt to the instruction set would help, and I sadly replied that
that bit of codel was totally invisible on a trace.....

I really like(d) mips. ton of registers, better instruction set than
arm (IMHO), no foolish processor extensions.

On Wed, Nov 28, 2018 at 10:26 AM David Collier-Brown <davec-b at rogers.com> wrote:
>
> On 2018-11-28 11:55 a.m., Dave Taht wrote:
>
> > Thank you for that. I do have a long standing dream of a single chip
> > wifi router, with the lowest SNR possible, and the minimum number of
> > pins coming off of it. I'd settle for 32MB of (static?) ram on chip as
> > that has proven sufficient to date to drive 802.11n....
> >
> > which would let you get rid of both the L2 and L1 cache. That said, I
> > think the cost of 32MB of on-chip static ram remains a bit high, and
> > plugging it into a mips cpu, kind of silly. Someday there will be a case
> > to just doing everything on a single chip, but...
>
> I could see 32MB or more of fast memory on-chip as being attractive when
> one is fighting with diminishing returns in CPU speed and program
> parallelizability.
>
> In the past that might have excited MIPS, but these days less so. Maybe
> ARM? IBM?
>
> --dave
>
> --
> David Collier-Brown,         | Always do right. This will gratify
> System Programmer and Author | some people and astonish the rest
> davecb at spamcop.net           |                      -- Mark Twain
>
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-- 

Dave Täht
CTO, TekLibre, LLC
http://www.teklibre.com
Tel: 1-831-205-9740