[Cake] Latency target curiosity

Kevin Darbyshire-Bryant kevin at darbyshire-bryant.me.uk
Thu May 7 03:58:01 EDT 2020

Hi All,

As some of you are aware, I’ve been working on ’near live’ graphing of Cake’s stats under Openwrt, basically taking the output of ’tc -s -j qdisc foo’ and putting in relevant graphs.

A curiosity has arisen:  I use diffserv4 mode on a 20Mbit egress link.  Bulk tin has ‘capacity’ threshold of 1.2Mbit and because it’s a slow ’tin', the default target & interval values get overridden to 14.6ms and 109.6ms respectively.  The 3 other tins are 5ms & 100ms defaults.

I have a backup job that bulk uploads 5 simultaneous flows to Onedrive.  The sparse_delay, average_delay & peak_delay figures settle on 32, 38 & 43 ms respectively with around 9 drops per second on that tin.

I’m curious as to why the reported delays are over double the target latency?


Kevin D-B

gpg: 012C ACB2 28C6 C53E 9775  9123 B3A2 389B 9DE2 334A

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