[Cerowrt-devel] trivial 6in4 fix(?)

[Toke Høiland-Jørgensen]

Sebastian Moeller <moeller0 at gmx.de> writes:

> I fully believe you that it is flat (graph did not make it into my
> inbox…)

Heh. May have forgotten to attach it... Should be there now...

> So that looks like PTM. Good! But beware the expected step size
> depends on your down and uplink speeds, at VDSL I would only expect a
> very tiny increase (basically the time it takes to see an additional
> ATM cell back and forth, (RTT step per ATM cell in milliseconds =
> (53*8 / line.down.bit + 53*8 / line.up.bit ) * 1000); this means that
> potentially a large sample size per ping packet size is required to be
> reasonably sure that there is no step....

Right, well in my case that comes out as something like 0.05 ms, which
is way below the measuring accuracy of my ping test (lowest mdev as
reported by ping is 0.7ms; highest is 3.3). So I guess testing is not
really going to be viable in this case. But then perhaps it's not going
to make much of a difference either way in this case?

> Hence in theory using a saturating load and measuring the latencies
> for different overhead values should still work. I wonder whether rrul
> might just be the right probe? If you go that route I would be
> delighted to learn the outcome :). Sorry to be of no more help here.

Right. That seems reasonable. However, it also seems to require a bit
more testing than I really have the time to spare right now, so I think
I'll defer it for the time being. I wonder if it would be possible to
persuade my ISP to set up a netperf server to test against...

Either way, thanks for your insight; I'll be sure to ping you if I come
up with something more conclusive... :)

-Toke

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