[Cerowrt-devel] tp-link 4300 evaluation
dave.taht at gmail.com
Sun May 26 08:08:54 EDT 2013
I am still on a quest to find a suitable netgear 3800 replacement. Paul
Vixie found the same chipset (I hope!)
being marketed as the WNDR3800-100NAS
so I have less fear about having to make the switch.
That said there are a few products on the market from buffalo and tplink
that are readily available on shelves today that seemed to be worth trying.
esr and I picked up a tp-link 4300 (89 retail) for evaluation yesterday. At
first glance it looked like a substantial update to the wndr3800 as it has
a two generation leap forward on the chipset, using the Atheros AR9344 rev
2, which features the MIPs 74k processor, which supposedly is twice as fast
as the 24k in the wndr3800. The box runs at a lower clock rate (540Mhz)
than the netgear 3800 (680), but I figured the better processor would win,
even if it got most of its theoretical win from an overly deep cpu pipeline.
I built openwrt for it, as I haven't built pure openwrt in a while... and
this device only has 8MB of flash, and I didn't
feel like stripping down cerowrt at the time.
+ There is a new skin for the luci gui which is quite nice, I don't know
why I haven't been using it.
+ It was neat to see the ipv6 relay thing work
+ Procd worked for the first time (I've been trying to switch to this in
cero for a while)
- Then I started poking into the forwarding performance...
Cerowrt regularly achieves 300+Mbit of ethernet forwarding performance in
netperf. the tplink barely gets 130. the marketing for the tplink calls it
a "n750" adding up the max theoretical values for the wifi channels, but I
doubt, given what I get on ethernet, that it even comes close to that in
It turns out on the tplink there is only one ethernet chip, which is
vlan-ed from the internal switch to the external port, instead of the two
that are in the wndr3800.
Now, there are quite a few differences between the software loads of
openwrt and of cerowrt - notably the openwrt build is bridged to the wifi
(I turned off the bridge, no difference in performance), and the default
atheros build currently has some de-optimizations in it to handle unaligned
access to packets that I don't think are needed on this later chipset,
but... it currently looks like in the quest for cost reduction, this step
forward to "modern" hardware is actually a large step backwards.
Fixing bufferbloat with cerowrt:
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