[Cerowrt-devel] trying to make sense of what switch vendors say wrt buffer bloat

[Mikael Abrahamsson]

On Mon, 6 Jun 2016, Jonathan Morton wrote:

> At 100ms buffering, their 10Gbps switch is effectively turning any DC 
> it’s installed in into a transcontinental Internet path, as far as peak 
> latency is concerned.  Just because RAM is cheap these days…

Nono, nononononono. I can tell you they're spending serious money on 
inserting this kind of buffering memory into these kinds of devices. 
Buying these devices without deep buffers is a lot lower cost.

These types of switch chips either have on-die memory (usually 16MB or 
less), or they have very expensive (a direct cost of lowered port density) 
off-chip buffering memory.

Typically you do this:

ports ---|-------
ports ---|      |
ports ---| chip |
ports ---|-------

Or you do this

ports ---|------|---buffer
ports ---| chip |---TCAM
          --------

or if you do a multi-linecard-device

ports ---|------|---buffer
          | chip |---TCAM
          --------
             |
         switch fabric

(or any variant of them)

So basically if you want to buffer and if you want large L2-L4 lookup 
tables, you have to sacrifice ports. Sacrifice lots of ports.

So never say these kinds of devices add buffering because RAM is cheap. 
This is most definitely not why they're doing it. Buffer memory for them 
is EXTREMELY EXPENSIVE.

-- 
Mikael Abrahamsson    email: swmike at swm.pp.se